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SN74LS147JDS PDF预览

SN74LS147JDS

更新时间: 2024-11-12 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 运算电路逻辑集成电路光电二极管编码器
页数 文件大小 规格书
7页 234K
描述
LS SERIES, 9-BIT ENCODER, CDIP16, CERAMIC, DIP-16

SN74LS147JDS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.17
Is Samacsys:N其他特性:9 TO 4 LINE PRIORITY ENCODER
系列:LSJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
逻辑集成电路类型:ENCODER位数:9
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):23 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74LS147JDS 数据手册

 浏览型号SN74LS147JDS的Datasheet PDF文件第2页浏览型号SN74LS147JDS的Datasheet PDF文件第3页浏览型号SN74LS147JDS的Datasheet PDF文件第4页浏览型号SN74LS147JDS的Datasheet PDF文件第5页浏览型号SN74LS147JDS的Datasheet PDF文件第6页浏览型号SN74LS147JDS的Datasheet PDF文件第7页 
SN54/74LS147  
SN54/74LS148  
SN54/74LS748  
10-LINE-TO-4-LINE  
AND 8-LINE-TO-3-LINE  
PRIORITY ENCODERS  
The SN54/74LS147 and the SN54/74LS148 are Priority Encoders. They  
provide priority decoding of the inputs to ensure that only the highest order  
data line is encoded. Both devices have data inputs and outputs which are  
active at the low logic level.  
The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied  
decimal zero condition does not require an input condition because zero is  
encoded when all nine data lines are at a high logic level.  
10-LINE-TO-4-LINE  
AND 8-LINE-TO-3-LINE  
PRIORITY ENCODERS  
LOW POWER SCHOTTKY  
The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By  
providing cascading circuitry (Enable Input EI and Enable Output EO) octal  
expansion is allowed without needing external circuitry.  
The SN54/74LS748 is a proprietary Motorola part incorporating a built-in  
deglitcher network which minimizes glitches on the GS output. The glitch  
occurs on the negative going transition of the EI input when data inputs 0–7  
are at logical ones.  
The only dc parameter differences between the LS148 and the LS748 are  
that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on  
the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a  
fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
The only ac difference is that t  
45 ns.  
from EI to EO is changed from 40 to  
PHL  
16  
SN54/74LS147  
1
(TOP VIEW)  
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
SN54/74LS148  
SN54/74LS748  
(TOP VIEW)  
FAST AND LS TTL DATA  
5-245  

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