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SN74LS00N-00 PDF预览

SN74LS00N-00

更新时间: 2024-11-04 19:25:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
25页 1238K
描述
LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14

SN74LS00N-00 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09系列:LS
JESD-30 代码:R-PDIP-T14长度:19.305 mm
负载电容(CL):15 pF逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):4.4 mA
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN74LS00N-00 数据手册

 浏览型号SN74LS00N-00的Datasheet PDF文件第2页浏览型号SN74LS00N-00的Datasheet PDF文件第3页浏览型号SN74LS00N-00的Datasheet PDF文件第4页浏览型号SN74LS00N-00的Datasheet PDF文件第5页浏览型号SN74LS00N-00的Datasheet PDF文件第6页浏览型号SN74LS00N-00的Datasheet PDF文件第7页 
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003  
D
Package Options Include Plastic  
Small-Outline (D, NS, PS), Shrink  
Small-Outline (DB), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J) DIPs  
D
Also Available as Dual 2-Input  
Positive-NAND Gate in Small-Outline (PS)  
Package  
SN5400 . . . J PACKAGE  
SN54LS00, SN54S00 . . . J OR W PACKAGE  
SN7400, SN74S00 . . . D, N, OR NS PACKAGE  
SN74LS00 . . . D, DB, N, OR NS PACKAGE  
(TOP VIEW)  
SN74LS00, SN74S00 . . . PS PACKAGE  
(TOP VIEW)  
V
2B  
2A  
2Y  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
2
3
4
8
7
6
5
1A  
1B  
1Y  
CC  
4B  
4A  
4Y  
3B  
3A  
3Y  
GND  
2Y  
GND  
8
SN5400 . . . W PACKAGE  
(TOP VIEW)  
SN54LS00, SN54S00 . . . FK PACKAGE  
(TOP VIEW)  
1A  
1B  
1Y  
4Y  
4B  
4A  
GND  
3B  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
3
2 1 20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
V
17  
16  
15  
14  
CC  
2Y  
2A  
2B  
3A  
3Y  
NC  
2B  
8
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢍꢌ ꢓ ꢋꢉ ꢖ ꢒꢑ ꢓ ꢁ ꢋ ꢊꢒꢊ ꢗꢘ ꢙ ꢚꢛ ꢜ ꢝꢞ ꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞ ꢗꢚꢘ ꢦꢝ ꢞꢢ ꢧ  
ꢍꢛ ꢚ ꢦꢡꢠ ꢞ ꢟ ꢠ ꢚꢘ ꢙꢚ ꢛ ꢜ ꢞ ꢚ ꢟ ꢣꢢ ꢠ ꢗꢙ ꢗꢠꢝ ꢞꢗ ꢚꢘꢟ ꢣꢢ ꢛ ꢞꢨ ꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢒꢢꢩ ꢝꢟ ꢑꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ  
ꢟ ꢞ ꢝ ꢘꢦ ꢝ ꢛꢦ ꢪ ꢝ ꢛꢛ ꢝ ꢘ ꢞꢫꢧ ꢍꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚꢘ ꢣꢛ ꢚꢠ ꢢꢟ ꢟꢗ ꢘꢬ ꢦꢚꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
Copyright 2003, Texas Instruments Incorporated  
ꢓ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢑ ꢆꢐ ꢍꢌ ꢮ ꢐꢯꢰꢂ ꢯꢂꢅ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢓ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢅ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
ꢣ ꢛ ꢚꢠꢢ ꢟꢟꢗ ꢘꢬ ꢦ ꢚꢢꢟ ꢘ ꢚꢞ ꢘ ꢢꢠꢢꢟ ꢟꢝꢛ ꢗ ꢥꢫ ꢗ ꢘꢠꢥ ꢡ ꢦꢢ ꢞꢢꢟ ꢞꢗꢘ ꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢧ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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