Datasheet > SN74HCT165_V01

SN74HCT165_V01

更新时间： 2024-10-02 02:52:15

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德州仪器 - TI		/
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描述
SN74HCT165 8-Bit Parallel-Load Shift Registers

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SN74HCT165_V01 数据手册

SN74HCT165

SCLS881A – OCTOBER 2021 – REVISED DECEMBER 2021

SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features

3 Description

•

LSTTL input logic compatible

– V_IL(max)= 0.8 V, V_IH(min)= 2 V

CMOS input logic compatible

– I_I≤ 1 µA at V_OL, V_OH

The SN74HCT165 is a parallel- or serial-in, serial-out

8-bit shift register. Parallel-in access to each stage is

provided by eight individual direct data (A-H) inputs

that are enabled by a low level at the shift/load

(SH/LD) input. The SN74HCT165 also features a

clock-inhibit (CLK INH) function and a complementary

serial (Q _H) output.

•

4.5 V to 5.5 V operation

Supports fanout up to 10 LSTTL loads

Direct overriding load (data) inputs

Gated clock inputs

Extended ambient temperature range: –40°C to

+125°C, T_A

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

SN74HCT165PW

TSSOP (16)

5.00 mm × 4.40 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Increase the number of inputs on a microcontroller

SH/LD

5 Additional

Shift Register

Stages

Q_H

SER

CLK INH

CLK

Positive Logic Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...24

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SN74HCT237DW3	TI	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,HCT-CMOS,SOP,16PIN,PLASTIC
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