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SN74HCT240DWR-00 PDF预览

SN74HCT240DWR-00

更新时间： 2024-11-20 14:44:51
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
19页 857K
描述
HCT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20

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中文翻译

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SN74HCT240DWR-00 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.08系列：HCT
JESD-30 代码：R-PDSO-G20长度：12.8 mm
负载电容（CL）：150 pF逻辑集成电路类型：BUS DRIVER
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：53 ns认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74HCT240DWR-00 数据手册

 浏览型号SN74HCT240DWR-00的Datasheet PDF文件第2页浏览型号SN74HCT240DWR-00的Datasheet PDF文件第3页浏览型号SN74HCT240DWR-00的Datasheet PDF文件第4页浏览型号SN74HCT240DWR-00的Datasheet PDF文件第5页浏览型号SN74HCT240DWR-00的Datasheet PDF文件第6页浏览型号SN74HCT240DWR-00的Datasheet PDF文件第7页 
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SCLS174E − MARCH 1984 − REVISED AUGUST 2003  
SN54HCT240 . . . J OR W PACKAGE  
SN74HCT240 . . . DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
High-Current Outputs Drive Up To 15  
LSTTL Loads  
D
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 12 ns  
pd  
6-mA Output Drive at 5 V  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
CC  
19 2OE  
18 1Y1  
17 2A4  
16 1Y2  
15 2A3  
14 1Y3  
13 2A2  
12 1Y4  
11 2A1  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
description/ordering information  
GND 10  
These octal buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters. The ’HCT240 devices are organized  
as two 4-bit buffers/drivers with separate  
output-enable (OE) inputs. When OE is low, the  
device passes inverted data from the A inputs to  
the Y outputs. When OE is high, the outputs are  
in the high-impedance state.  
SN54HCT240 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT240N  
SN74HCT240N  
SN74HCT240DW  
SN74HCT240DWR  
SN74HCT240NSR  
SN74HCT240PW  
SN74HCT240PWR  
SN74HCT240PWT  
SNJ54HCT240J  
SOIC − DW  
SOP − NS  
HCT240  
HCT240  
−40°C to 85°C  
TSSOP − PW  
HT240  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT240J  
SNJ54HCT240W  
SNJ54HCT240W  
SNJ54HCT240FK  
−55°C to 125°C  
SNJ54HCT240FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

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