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SN74HC594N-00 PDF预览

SN74HC594N-00

更新时间： 2024-11-23 15:52:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 964K
描述
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16

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中文翻译

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SN74HC594N-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.54其他特性：PARALLEL OUTPUT IS REGISTERED; ASYNCHRONOUS CLEAR FOR STORAGE REGISTER
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-PDIP-T16长度：19.305 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：37 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：20 MHzBase Number Matches：1

SN74HC594N-00 数据手册

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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
Low Input Current of 1 µA Max  
8-Bit Serial-In, Parallel-Out Shift Registers  
With Storage  
High-Current Outputs Can Drive Up To  
15 LSTTL Loads  
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 15 ns  
pd  
6-mA Output Drive at 5 V  
D
D
Independent Direct Overriding Clears on  
Shift and Storage Registers  
CC  
Independent Clocks for Both Shift and  
Storage Registers  
SN54HC594 . . . J OR W PACKAGE  
SN74HC594 . . . D, DW, OR N PACKAGE  
(TOP VIEW)  
SN54HC594 . . . FK PACKAGE  
(TOP VIEW)  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
B
Q
3
2
1
20 19  
18  
C
D
A
SER  
RCLR  
NC  
Q
4
5
6
7
8
D
Q
SER  
Q
17  
16  
15  
E
Q
RCLR  
RCLK  
SRCLK  
SRCLR  
E
NC  
Q
F
RCLK  
Q
F
Q
G
14 SRCLK  
9 10 11 12 13  
Q
G
Q
H
GND  
Q
H′  
NC − No internal connection  
description/ordering information  
The ’HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage  
register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and  
storage registers. A serial (Q ) output is provided for cascading purposes.  
H′  
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks  
are connected together, the shift register always is one count pulse ahead of the storage register.  
The parallel (Q −Q ) outputs have high-current capability. Q is a standard output.  
A
H
H′  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Tube of 40  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC594N  
SN74HC594N  
SN74HC594D  
SN74HC594DR  
SN74HC594DT  
SN74HC594DW  
SN74HC594DWR  
SNJ54HC594J  
SNJ54HC594W  
SNJ54HC594FK  
HC594  
−40°C to 85°C  
−55°C to 125°C  
SOIC − DW  
HC594  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC594J  
SNJ54HC594W  
SNJ54HC594FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

中文翻译

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