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SN74HC540DBR PDF预览

SN74HC540DBR

更新时间： 2024-11-22 05:04:47
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
15页 508K
描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74HC540DBR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP20,.3
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.61
控制类型：ENABLE LOW系列：HC/UH
JESD-30 代码：R-PDSO-G20长度：7.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP20,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 VProp。Delay @ Nom-Sup：25 ns
传播延迟（tpd）：188 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

SN74HC540DBR 数据手册

 浏览型号SN74HC540DBR的Datasheet PDF文件第2页浏览型号SN74HC540DBR的Datasheet PDF文件第3页浏览型号SN74HC540DBR的Datasheet PDF文件第4页浏览型号SN74HC540DBR的Datasheet PDF文件第5页浏览型号SN74HC540DBR的Datasheet PDF文件第6页浏览型号SN74HC540DBR的Datasheet PDF文件第7页 
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SCLS007D − MARCH 1984 − REVISED AUGUST 2003  
SN54HC540 . . . J OR W PACKAGE  
SN74HC540 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Drive Bus  
Lines Directly or Up To 15 LSTTL Loads  
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 8 ns  
pd  
6-mA Output Drive at 5 V  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
Y1  
1
2
3
4
5
6
7
8
9
20  
19  
18  
CC  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
13 Y6  
12 Y7  
11 Y8  
Low Input Current of 1 µA Max  
Data Flow-Through Pinout (All Inputs on  
Opposite Side From Outputs)  
description/ordering information  
GND 10  
These octal buffers and line drivers feature the  
performance of the popular ’HC240 series and  
offer a pinout with inputs and outputs on opposite  
sides of the package. This arrangement greatly  
facilitates printed circuit board layout.  
SN54HC540 . . . FK PACKAGE  
(TOP VIEW)  
The 3-state control gate is a 2-input NOR. If either  
output-enable (OE1 or OE2) input is high, all eight  
outputs are in the high-impedance state. The  
’HC540 devices provide inverted data at the  
outputs.  
3
2
1
20 19  
18  
Y1  
Y2  
Y3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15 Y4  
14  
Y5  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HC540N  
SN74HC540N  
SN74HC540DW  
SN74HC540DWR  
SN74HC540NSR  
SN74HC540DBR  
SN74HC540PW  
SN74HC540PWR  
SN74HC540PWT  
SNJ54HC540J  
SOIC − DW  
HC540  
SOP − NS  
HC540  
HC540  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC540  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC540J  
SNJ54HC540W  
SNJ54HC540FK  
SNJ54HC540W  
SNJ54HC540FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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