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SN74HC5138

更新时间： 2024-11-22 12:30:23
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
20页 1153K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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中文翻译

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SN74HC5138 数据手册

 浏览型号SN74HC5138的Datasheet PDF文件第2页浏览型号SN74HC5138的Datasheet PDF文件第3页浏览型号SN74HC5138的Datasheet PDF文件第4页浏览型号SN74HC5138的Datasheet PDF文件第5页浏览型号SN74HC5138的Datasheet PDF文件第6页浏览型号SN74HC5138的Datasheet PDF文件第7页 
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SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003  
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
D
D
Low Power Consumption, 80-µA Max I  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
CC  
Typical t = 17 ns  
pd  
4-mA Output Drive at 5 V  
D
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
SN54HCT138 . . . J OR W PACKAGE  
SN74HCT138 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HCT138 . . . FK PACKAGE  
(TOP VIEW)  
A
B
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
3
2
1
20 19  
18  
Y0  
Y1  
Y2  
Y1  
Y2  
NC  
C
G2A  
NC  
4
5
6
7
8
C
17  
16  
G2A  
G2B  
G1  
12 Y3  
15 Y3  
14  
9 10 11 12 13  
G2B  
G1  
11  
10  
9
Y4  
Y5  
Y6  
Y4  
Y7  
GND  
NC − No internal connection  
description/ordering information  
The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications  
requiring very short propagation delay times. In high-performance memory systems, these decoders can  
minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable  
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical  
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HCT138N  
SN74HCT138N  
SN74HCT138D  
SN74HCT138DR  
SN74HCT138DT  
SN74HCT138NSR  
SN74HCT138PW  
SN74HCT138PWR  
SN74HCT138PWT  
SNJ54HCT138J  
SNJ54HCT138W  
SNJ54HCT138FK  
SOIC − D  
SOP − NS  
HCT138  
HCT138  
−40°C to 85°C  
TSSOP − PW  
HT138  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT138J  
SNJ54HCT138W  
SNJ54HCT138FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

中文翻译

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