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SN74HC373AN PDF预览

SN74HC373AN

更新时间: 2024-11-02 12:02:43
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
23页 1206K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN74HC373AN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.68Is Samacsys:N
JESD-30 代码:R-PDIP-T20JESD-609代码:e4
负载电容(CL):50 pF逻辑集成电路类型:JBAR-KBAR FLIP-FLOP
最大I(ol):0.006 A位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:31 ns
认证状态:Not Qualified子类别:FF/Latches
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

SN74HC373AN 数据手册

 浏览型号SN74HC373AN的Datasheet PDF文件第2页浏览型号SN74HC373AN的Datasheet PDF文件第3页浏览型号SN74HC373AN的Datasheet PDF文件第4页浏览型号SN74HC373AN的Datasheet PDF文件第5页浏览型号SN74HC373AN的Datasheet PDF文件第6页浏览型号SN74HC373AN的Datasheet PDF文件第7页 
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
6-mA Output Drive at 5 V  
High-Current 3-State True Outputs Can  
Drive Up To 15 LSTTL Loads  
D
D
Low Input Current of 1 µA Max  
Eight High-Current Latches in a Single  
Package  
D
Low Power Consumption, 80-µA Max I  
CC  
D
Typical t = 13 ns  
pd  
D
Full Parallel Access for Loading  
SN54HC373 . . . J OR W PACKAGE  
SN74HC373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HC373 . . . FK PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 LE  
15 6Q  
14  
9 10 11 12 13  
6D  
GND 10  
description/ordering information  
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is  
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that  
were set up at the D inputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HC373N  
SN74HC373N  
SN74HC373DW  
SN74HC373DWR  
SN74HC373NSR  
SN74HC373DBR  
SN74HC373PW  
SN74HC373PWR  
SN74HC373PWT  
SNJ54HC373J  
SOIC − DW  
HC373  
SOP − NS  
HC373  
HC373  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC373  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC373J  
SNJ54HC373W  
SNJ54HC373FK  
−55°C to 125°C  
SNJ54HC373W  
SNJ54HC373FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢌꢑ ꢎꢍ ꢭ ꢑꢆꢮꢂ ꢆꢂꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢉ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢈ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC373AN 替代型号

型号 品牌 替代类型 描述 数据表
MM74HC373N FAIRCHILD

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