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SN74HC138N-10 PDF预览

SN74HC138N-10

更新时间： 2024-11-02 21:18:11
品牌 Logo 应用领域
德州仪器 - TI 驱动输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
22页 1174K
描述
HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16

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SN74HC138N-10 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.49
其他特性：3 ENABLE INPUTS系列：HC/UH
JESD-30 代码：R-PDIP-T16长度：19.305 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：45 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74HC138N-10 数据手册

 浏览型号SN74HC138N-10的Datasheet PDF文件第2页浏览型号SN74HC138N-10的Datasheet PDF文件第3页浏览型号SN74HC138N-10的Datasheet PDF文件第4页浏览型号SN74HC138N-10的Datasheet PDF文件第5页浏览型号SN74HC138N-10的Datasheet PDF文件第6页浏览型号SN74HC138N-10的Datasheet PDF文件第7页 
SN54HC138, SN74HC138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC138 . . . J OR W PACKAGE  
SN74HC138 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Targeted Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
A
B
C
VCC  
Y0  
Y1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Low Power Consumption, 80-μA Max I  
CC  
G2A  
G2B  
G1  
Y7  
GND  
Y2  
Typical t = 15 ns  
pd  
12 Y3  
4-mA Output Drive at 5 V  
11  
10  
9
Y4  
Y5  
Y6  
Low Input Current of 1 μA Max  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
SN54HC138 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’HC138 devices are designed to be used in  
high-performance memory-decoding or data-  
routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, these decoders can be used to  
minimize the effects of system decoding. When  
employed with high-speed memories utilizing a  
fast enable circuit, the delay times of these  
decoders and the enable time of the memory are  
usually less than the typical access time of the  
memory. This means that the effective system  
delay introduced by the decoders is negligible.  
3
2
1
20 19  
18  
Y1  
Y2  
NC  
C
G2A  
NC  
G2B  
G1  
4
5
6
7
8
17  
16  
15 Y3  
14  
9 10 11 12 13  
Y4  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC138N  
SN74HC138N  
SN74HC138D  
SN74HC138DR  
SN74HC138DT  
SN74HC138NSR  
SN74HC138DBR  
SN74HC138PW  
SN74HC138PWR  
SN74HC138PWT  
SNJ54HC138J  
HC138  
SOP − NS  
HC138  
HC138  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC138  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC138J  
SNJ54HC138W  
SNJ54HC138FK  
SNJ54HC138W  
SNJ54HC138FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...22

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