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SN74HC138QPWRG4Q1 PDF预览

SN74HC138QPWRG4Q1

更新时间: 2024-01-07 00:18:38
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 814K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SN74HC138QPWRG4Q1 数据手册

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SN74HC138-Q1  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCLS533A − AUGUST 2003 − REVISED SEPTEMBER 2008  
D OR PW PACKAGE  
(TOP VIEW)  
D
D
Qualified for Automotive Applications  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
A
B
VCC  
Y0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
D
Targeted Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
C
Y1  
G2A  
G2B  
G1  
Y7  
GND  
Y2  
12 Y3  
D
D
D
D
D
D
D
2-V to 6-V V Operation  
11  
10  
9
CC  
Y4  
Y5  
Y6  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 15 ns  
pd  
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
description/ordering information  
The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications  
requiring very short propagation delay times. In high-performance memory systems, this decoder can be used  
to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable  
circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access  
time of the memory. This means that the effective system delay introduced by the decoders is negligible.  
The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two  
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.  
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
SOIC − D  
Tape and reel  
Tape and reel  
SN74HC138QDRQ1  
SN74HC138QPWRQ1  
HC138Q1  
HC138Q1  
−40°C to 125°C  
TSSOP − PW  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at www.ti.com.  
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2008, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC138QPWRG4Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC139PWR TI

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