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SN74F520DW-00R PDF预览

SN74F520DW-00R

更新时间: 2024-11-24 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 80K
描述
F/FAST SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, PDSO20

SN74F520DW-00R 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77其他特性:WITH PULLUP RESISTORS ON Q INPUTS
系列:F/FASTJESD-30 代码:R-PDSO-G20
长度:12.8 mm逻辑集成电路类型:IDENTITY COMPARATOR
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):10.3 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

SN74F520DW-00R 数据手册

 浏览型号SN74F520DW-00R的Datasheet PDF文件第2页浏览型号SN74F520DW-00R的Datasheet PDF文件第3页浏览型号SN74F520DW-00R的Datasheet PDF文件第4页浏览型号SN74F520DW-00R的Datasheet PDF文件第5页 
ꢀꢁ ꢂꢃ ꢄ ꢂ ꢅ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢃꢄꢂ ꢅꢆ  
ꢊ ꢋꢌꢍ ꢎꢈ ꢍꢏꢐ ꢁꢎ ꢍꢎ ꢑꢈꢒ ꢓꢔ ꢕꢖꢗ ꢖꢎꢓ ꢗꢀ  
SDFS081A − MARCH 1987 − REVISED OCTOBER 1993  
SN54F520 . . . J PACKAGE  
SN74F520 . . . DW OR N PACKAGE  
(TOP VIEW)  
Compares Two 8-Bit Words  
20-kPullup Resistors on Q Inputs  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
OE  
P0  
V
CC  
P = Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Q0  
Q7  
P1  
P7  
description  
Q1  
Q6  
P2  
P6  
These identity comparators perform comparisons  
on two 8-bit binary or BCD words. They provide  
P = Q outputs. The F520 features 20-kpullup  
termination resistors on the Q inputs for analog or  
switch data.  
Q2  
Q5  
P3  
Q3  
13 P5  
12 Q4  
11  
GND  
P4  
The SN54F520 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F520 is characterized for  
operation from 0°C to 70°C.  
SN54F520 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
3
2
1
20 19  
18  
INPUTS  
OUTPUT  
P = Q  
Q7  
P7  
Q6  
P6  
Q5  
P1  
Q1  
P2  
Q2  
P3  
4
5
6
7
8
P, Q  
OE  
L
17  
16  
15  
14  
P = Q  
P Q  
X
L
H
H
X
H
9 10 11 12 13  
logic symbol  
COMP  
1
OE  
2
P0  
0
4
P1  
6
P2  
8
P3  
11  
P
P4  
13  
P5  
15  
P6  
17  
P7  
3
7
0
19  
P = Q  
1P = Q  
Q0  
5
Q1  
7
Q2  
9
Q3  
12  
Q4  
14  
Q5  
16  
Q6  
18  
Q7  
Q
7
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
ꢎꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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