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SN74CBTLV3861DWG4 PDF预览

SN74CBTLV3861DWG4

更新时间: 2024-11-25 04:28:03
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德州仪器 - TI 开关
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14页 493K
描述
LOW-VOLTAGE 10-BIT FET BUS SWITCH

SN74CBTLV3861DWG4 数据手册

 浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第2页浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第3页浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第4页浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第5页浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第6页浏览型号SN74CBTLV3861DWG4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ  
ꢇ ꢍꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢌ ꢓ ꢏꢅꢔ ꢆ ꢕ ꢒꢆ ꢅꢖ ꢀ ꢀ ꢎꢔ ꢆꢄ ꢗ  
SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003  
DBQ, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
5-Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
I
Supports Partial-Power-Down Mode  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
A1  
V
CC  
off  
Operation  
2
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
3
A2  
A3  
A4  
A5  
Flow-Through Architecture Optimizes PCB  
Layout  
4
5
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
6
7
A6  
A7  
A8  
A9  
8
description/ordering information  
9
The SN74CBTLV3861 provides ten bits of  
high-speed bus switching. The low on-state  
resistance of the switch allows connections to be  
made with minimal propagation delay.  
10  
11  
12  
A10  
GND  
NC − No internal connection  
The device is organized as one 10-bit bus switch.  
When output enable (OE) is low, the 10-bit bus  
switch is on, and port A is connected to port B.  
When OE is high, the switch is open, and the  
high-impedance state exists between the two  
ports.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QSOP − DBQ  
SOIC − DW  
Tape and reel  
Tube  
SN74CBTLV3861DBQR  
SN74CBTLV3861DW  
SN74CBTLV3861DWR  
SN74CBTLV3861NSR  
SN74CBTLV3861PWR  
SN74CBTLV3861DGVR  
CL861  
CBTLV3861  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
−40°C to 85°C  
SOP − NS  
CBTLV3861  
CL861  
TSSOP − PW  
TVSOP − DGV  
CL861  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUT  
FUNCTION  
OE  
L
A port = B port  
Disconnect  
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢘꢟ ꢞ ꢪꢥꢤ ꢢ ꢣ ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛꢝ ꢛꢤꢡ ꢢꢛ ꢞꢜꢣ ꢧꢦ ꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢆꢦꢭ ꢡꢣ ꢔꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ  
ꢣ ꢢ ꢡ ꢜꢪ ꢡ ꢟꢪ ꢮ ꢡ ꢟꢟ ꢡ ꢜ ꢢꢯꢫ ꢘꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞꢜ ꢧꢟ ꢞꢤ ꢦꢣ ꢣꢛ ꢜꢰ ꢪꢞꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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