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SN74CBTLV3861-Q1_15 PDF预览

SN74CBTLV3861-Q1_15

更新时间： 2024-11-28 02:58:47
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德州仪器 - TI /
页数 文件大小 规格书
7页 124K
描述
LOW-VOLTAGE 10-BIT FET BUS SWITCH

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SN74CBTLV3861-Q1_15 数据手册

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SCDS160A − MARCH 2004 − REVISED MAY 2004  
DW OR PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
†
D
Qualified for Automotive Applications  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
V
CC  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
2
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
3
4
5
D
D
D
D
D
5-Ω Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
6
7
I
Supports Partial-Power-Down Mode  
off  
8
Operation  
9
Flowthrough Architecture Optimizes PCB  
Layout  
10  
11  
12  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
GND  
†
NC − No internal connection  
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74CBTLV3861 provides ten bits of high-speed bus switching. The low on-state resistance of the switch  
allows connections to be made with minimal propagation delay.  
The device is organized as one 10-bit bus switch. When output enable (OE) is low, the 10-bit bus switch is on,  
and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists  
between the two ports.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − DW  
Tape and reel  
Tape and reel  
CCBTLV3861IDWRQ1  
CCBTLV3861IPWRQ1  
CL3861Q1  
CL3861Q1  
−40°C to 85°C  
TSSOP − PW  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUT  
FUNCTION  
OE  
L
A port = B port  
Disconnect  
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
ꢙꢠ ꢟ ꢫꢦꢥ ꢣ ꢤ ꢥ ꢟꢝ ꢞꢟ ꢠ ꢡ ꢣ ꢟ ꢤ ꢨꢧ ꢥ ꢜꢞ ꢜꢥꢢ ꢣꢜ ꢟꢝꢤ ꢨꢧ ꢠ ꢣꢭ ꢧ ꢣꢧ ꢠ ꢡꢤ ꢟꢞ ꢆꢧꢮ ꢢꢤ ꢕꢝꢤ ꢣꢠ ꢦꢡ ꢧꢝꢣ ꢤ  
ꢤ ꢣ ꢢ ꢝꢫ ꢢ ꢠꢫ ꢯ ꢢ ꢠꢠ ꢢ ꢝ ꢣꢰꢬ ꢙꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟꢝ ꢨꢠ ꢟꢥ ꢧꢤ ꢤꢜ ꢝꢱ ꢫꢟꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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