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SN74CBTLV16235DGGR

更新时间： 2024-09-13 13:00:03
品牌 Logo 应用领域
德州仪器 - TI 解复用器
页数 文件大小 规格书
8页 140K
描述
CBTLV/3B SERIES, 18 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

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SN74CBTLV16235DGGR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP64,.32,20
针数：64Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.31
系列：CBTLV/3BJESD-30 代码：R-PDSO-G64
长度：17 mm逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER
功能数量：18输入次数：1
输出次数：2端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP64,.32,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN74CBTLV16235DGGR 数据手册

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SCDS060F − MARCH 1998 − REVISED OCTOBER 2003  
DGG PACKAGE  
(TOP VIEW)  
D
D
D
D
4-Ω Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
I
Supports Partial-Power-Down Mode  
1A  
2B1  
2B2  
3A  
1B1  
1B2  
2A  
3B1  
3B2  
4A  
off  
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64  
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Operation  
2
Break-Before-Make Feature  
3
4
description/ordering information  
4B1  
4B2  
5A  
6B1  
6B2  
7A  
8B1  
8B2  
GND  
5
6
The SN74CBTLV16235 is an 18-bit 1-of-2 FET  
multiplexer/demultiplexer used in applications in  
which two separate data paths must be  
multiplexed onto, or demultiplexed from, a single  
path. This device can be used for memory  
interleaving, where two different banks of memory  
need to be addressed simultaneously.  
5B1  
5B2  
6A  
7B1  
7B2  
8A  
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18  
19  
20  
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23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
GND  
VCC  
9B1  
9B2  
10A  
11B1  
11B2  
12A  
13B1  
13B2  
14A  
15B1  
15B2  
16A  
17B1  
17B2  
18A  
GND  
S0  
The device is organized as a dual 9-bit 1-of-2  
multiplexer/demultiplexer with separate control  
inputs. It can be used as two 9-bit  
multiplexers/demultiplexers or as one 18-bit  
multiplexer/demultiplexer. Two select (S0 and S1)  
inputs control the data flow. When the test (T0 and  
T1) inputs are asserted, port A is connected to  
both ports B1 and B2. The control inputs can be  
driven with a low-voltage TTL or an SSTL_3  
driver.  
V
CC  
9A  
10B1  
10B2  
11A  
12B1  
12B2  
13A  
14B1  
14B2  
15A  
16B1  
16B2  
17A  
The SN74CBTLV16235 is specified by the  
break-before-make design to have no through  
current when switching directions.  
This  
device  
is  
fully  
specified  
for  
18B1  
18B2  
GND  
T0  
partial-power-down applications using I . The I  
off  
off  
feature ensures that damaging current will not  
backflow through the device when it is powered  
down. The device has isolation during power off.  
T1  
S1  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
−40°C to 85°C TSSOP − DGG Tape and reel  
SN74CBTLV16235GR  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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