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SN74AUP1G17DRLRG4

更新时间： 2024-11-29 05:24:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 456K
描述
LOW - POWER SINGLE SCHMITT-TRIGGLER BUFFER

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SN74AUP1G17DRLRG4 数据手册

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SCES579C – JUNE 2004 – REVISED NOVEMBER 2005  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
D
D
D
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
t
= 5.1 ns Max at 3.3 V  
pd  
I
= 0.9 µA Max  
CC  
Suitable for Point-to-Point Applications  
Low Dynamic-Power Consumption;  
= 4.4 pF Typ at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
C
pd  
D
Low Input Capacitance; C = 1.5 pF Typ  
i
Low Noise − Overshoot and Undershoot  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
D
<10% of V  
CC  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
D
D
D
Includes Schmitt-Trigger Inputs  
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
Optimized for 3.3-V Operation  
DCK PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
Y
1
2
3
5
GND  
A
NC  
V
Y
NC  
A
V
Y
1
2
3
5
CC  
CC  
1
2
3
5
4
NC  
A
V
Y
CC  
A
5
V
DNU  
CC  
4
GND  
4
GND  
DNU – Do not use  
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire V range  
CC  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
Switching Characteristics  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
†
at 25 MHz  
(µA)  
3.5  
3
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 2. Excellent Signal Integrity  
Figure 1. AUP−The Lowest-Power Family  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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SN74AUP1G17DRLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G17DRLR TI

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