SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
RGY PACKAGE
(TOP VIEW)
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I
Supports Partial-Power-Down Mode
off
Operation
1
14
Sub 1-V Operable
1D
1CLK
1PRE
1Q
13 2CLR
12 2D
2
3
4
5
6
Max t of 1.8 ns at 1.8-V
pd
Low Power Consumption, 10-µA Max I
11
10
9
2CLK
2PRE
2Q
CC
8-mA Output Drive at 1.8 V
1Q
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
7
8
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
Thisdualpositive-edge-triggeredD-typeflip-flopisoperationalat0.8-Vto2.7-VV ,butisdesignedspecifically
CC
for 1.65-V to 1.95-V V
operation.
CC
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop
for higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
–40°C to 85°C QFN – RGY
Tape and reel
SN74AUC74RGYR
MS74
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
H
L
Q
H
L
Q
L
H
L
X
X
H
L
H
H
H
H
↑
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265