Datasheet > SN74AUC74_07

SN74AUC74_07

更新时间： 2024-09-29 05:17:39

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
12页	560K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN74AUC74_07 数据手册

SN74AUC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

www.ti.com

SCES483A–AUGUST 2003–REVISED MARCH 2005

FEATURES

RGY PACKAGE

(TOP VIEW)

•

Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

•

I_offSupports Partial-Power-Down Mode

Operation

1CLK

1PRE

2CLR

•

Sub-1-V Operable

Max t_pdof 1.8 ns at 1.8 V

2CLK

2PRE

Low Power Consumption, 10-µA Max I_CC

±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed specifically

for 1.65-V to 1.95-V V_CCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for

higher frequencies, the CLR input overrides the PRE input when they are both low.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

QFN – RGY

Tape and reel

SN74AUC74RGYR

MS74

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

↑

Q₀

Q ₀

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

中文翻译

下载PDF

与SN74AUC74_07相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC74_09	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74AUC74_10	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74AUC74RGYR	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AUC74RGYRG4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74AUCH16244	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUCH16244_07	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUCH16244DGGR	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUCH16244DGVR	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUCH16244GQLR	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUCH16244ZQLR	TI	获取价格	16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

与SN74AUC74_07相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

24
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

22
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

21
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

34

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC74_07

SN74AUC74_07 数据手册

与SN74AUC74_07相关器件

与SN74AUC74_07相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC74_07

SN74AUC74_07 数据手册

与SN74AUC74_07相关器件

与SN74AUC74_07相关文章

您还可以找

您在本页遇到什么问题？