SN74AUC00

更新时间： 2024-02-24 11:26:24

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
8页	241K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATE

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SN74AUC00 数据手册

SN74AUC00

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

www.ti.com

SCES510A–NOVEMBER 2003–REVISED MARCH 2005

FEATURES

RGY PACKAGE

(TOP VIEW)

•

Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

•

I_offSupports Partial-Power-Down Mode

Operation

13 4B

•

Sub-1-V Operable

Max t_pdof 2 ns at 1.8 V

Low Power Consumption, 10-µA Max I_CC

±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for

1.65-V to 1.95-V V_CCoperation.

The SN74AUC00 devices perform the Boolean function Y = A B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

MS00

–40°C to 85°C

QFN – RGY

Tape and reel

SN74AUC00RGYR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(EACH GATE)

INPUTS

OUTPUT

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7 8

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