Datasheet > SN74AS303

SN74AS303

更新时间： 2024-11-13 21:55:35

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
7页	112K
描述
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

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SN74AS303 数据手册

CDC303

OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

SCAS323A – JULY 1990 – REVISED NOVEMBER 1995

D OR N PACKAGE

(TOP VIEW)

Replaces SN74AS303

Maximum Output Skew Between Same

Phase Outputs of 1 ns

CLR

GND

Maximum Pulse Skew of 1 ns

TTL-Compatible Inputs and Outputs

Center-Pin V

Minimize High-Speed Switching Noise

and GND Configurations

CLK

PRE

Package Options Include Plastic

Small-Outline (D) Package and Standard

Plastic (N) 300-mil DIPs

description

The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six

in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)

inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.

The CDC303 has output and pulse-skew parameters t

when a divide-by-two function is required.

and t

to ensure performance as a clock driver

sk(o)

sk(p)

The CDC303 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

PRE

CLK Q1–Q6 Q7–Q8

↑

†

This configuration does not persist when

PRE or CLR returns to its inactive (high)

level.

‡

logic symbol

PRE

CLK

CLR

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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