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SN74AS137D PDF预览

SN74AS137D

更新时间: 2024-11-14 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器锁存器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
15页 516K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

SN74AS137D 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N其他特性:ADDRESS LATCHES
系列:AS输入调节:STANDARD
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):24 mA
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

SN74AS137D 数据手册

 浏览型号SN74AS137D的Datasheet PDF文件第2页浏览型号SN74AS137D的Datasheet PDF文件第3页浏览型号SN74AS137D的Datasheet PDF文件第4页浏览型号SN74AS137D的Datasheet PDF文件第5页浏览型号SN74AS137D的Datasheet PDF文件第6页浏览型号SN74AS137D的Datasheet PDF文件第7页 
SN54ALS137A, SN74ALS137A, SN74AS137  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
WITH ADDRESS LATCHES  
SDAS203C – APRIL 1982 – REVISED JANUARY 1995  
SN54ALS137A . . . J PACKAGE  
SN74ALS137A, SN74AS137 . . . D OR N PACKAGE  
(TOP VIEW)  
Combines Decoder and 3-Bit Address  
Latch  
Incorporates Two Output Enables to  
Simplify Cascading  
A
B
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Package Options Include Plastic Small-  
Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
C
LE  
G2  
G1  
Y7  
description  
GND  
The SN54ALS137A, SN74ALS137A, and  
SN74AS137 are 3-line to 8-line decoders/  
demultiplexers with latches on the three address  
inputs. When the latch-enable (LE) input is low,  
the devices act as decoders/demultiplexers.  
When LE goes from low to high, the address  
present at the select (A, B, and C) inputs is stored  
in the latches. Further address changes are  
ignored as long as LE remains high. The  
output-enable controls (G1 and G2) control the  
outputs independently of the select or  
latch-enable inputs. All of the outputs are forced  
high if G1 is low or G2 is high. These devices are  
ideally suited for implementing glitch-free  
decoders in strobed (stored-address) applications  
in bus-oriented systems.  
SN54ALS137A . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18 Y1  
C
LE  
4
5
6
7
8
17  
16  
15  
14  
Y2  
NC  
Y3  
Y4  
NC  
G2  
G1  
9 10 11 12 13  
NC – No internal connection  
The SN54ALS137A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS137A and SN74AS137  
are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
ENABLE  
SELECT  
LE  
X
X
L
G1  
X
G2  
C
X
X
L
B
X
X
L
A
X
X
L
Y0  
H
H
L
Y1  
H
H
H
L
Y2  
H
H
H
H
L
Y3  
H
H
H
H
H
L
Y4  
H
H
H
H
H
H
L
Y5  
H
H
H
H
H
H
H
L
Y6  
H
H
H
H
H
H
H
H
L
Y7  
H
X
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
X
H
H
H
H
L
L
H
L
H
H
H
L
H
H
X
H
H
L
H
X
H
H
Outputs corresponding to stored address = L; all others = H  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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