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SN74AS138N3 PDF预览

SN74AS138N3

更新时间: 2024-11-14 22:13:43
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器逻辑集成电路光电二极管输入元件驱动
页数 文件大小 规格书
16页 523K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SN74AS138N3 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, PLASTIC, DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
Is Samacsys:N其他特性:2 ACTIVE-LOW AND 1 ACTIVE-HIGH ENABLE INPUT, SCHOTTKY-CLAMPED FOR HIGH PERFORMANCE
系列:AS输入调节:STANDARD
JESD-30 代码:R-PDIP-T16长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):20 mA传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74AS138N3 数据手册

 浏览型号SN74AS138N3的Datasheet PDF文件第2页浏览型号SN74AS138N3的Datasheet PDF文件第3页浏览型号SN74AS138N3的Datasheet PDF文件第4页浏览型号SN74AS138N3的Datasheet PDF文件第5页浏览型号SN74AS138N3的Datasheet PDF文件第6页浏览型号SN74AS138N3的Datasheet PDF文件第7页 
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SDAS055E – APRIL 1982 – REVISED JULY 1996  
SN54ALS138A, SN54AS138 . . . J PACKAGE  
SN74ALS138A, SN74AS138 . . . D OR N PACKAGE  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
(TOP VIEW)  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
A
B
C
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
G2A  
G2B  
G1  
Y7  
GND  
description  
The ALS138A and AS138 are 3-line to 8-line  
decoders/demultiplexers designed for high-  
performance memory-decoding or data-routing  
applications requiring very short propagation  
delay times. In high-performance systems, these  
devices can be used to minimize the effects of  
system decoding. When employed with  
high-speed memories with a fast enable circuit,  
thedelaytimesofthedecoderandtheenabletime  
of the memory are usually less than the typical  
access time of the memory. The effective system  
delayintroducedbytheSchottky-clampedsystem  
decoder is negligible.  
SN54ALS138A, SN54AS138 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18 Y1  
C
G2A  
NC  
4
5
6
7
8
17  
16  
15  
14  
Y2  
NC  
Y3  
Y4  
G2B  
G1  
9 10 11 12 13  
The conditions at the binary-select (A, B, and C)  
inputs and the three enable (G1, G2A, and G2B)  
inputs select one of eight output lines. Two  
active-low and one active-high enable inputs  
NC – No internal connection  
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without  
external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input  
for demultiplexing applications.  
The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range  
of 55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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