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SN74AS131AN PDF预览

SN74AS131AN

更新时间: 2024-11-15 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 解复用器双倍数据速率
页数 文件大小 规格书
6页 109K
描述
3-Line To 8-Line Decoders/Demultiplexers With Address Registers 16-PDIP 0 to 70

SN74AS131AN 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, PLASTIC, DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.87
Is Samacsys:N其他特性:ADDRESS REGISTERS
系列:AS输入调节:STANDARD
JESD-30 代码:R-PDIP-T16长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大频率@ Nom-Sup:100000000 Hz功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):30 mA传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74AS131AN 数据手册

 浏览型号SN74AS131AN的Datasheet PDF文件第2页浏览型号SN74AS131AN的Datasheet PDF文件第3页浏览型号SN74AS131AN的Datasheet PDF文件第4页浏览型号SN74AS131AN的Datasheet PDF文件第5页浏览型号SN74AS131AN的Datasheet PDF文件第6页 
ꢀꢁꢂ ꢃꢄ ꢀꢅ ꢆꢅ ꢄ  
ꢆ ꢇꢈ ꢉꢁꢊ ꢋꢌꢍ ꢋꢎ ꢇꢈ ꢉꢁ ꢊꢋꢏꢊ ꢐꢍ ꢏꢊꢑꢒ ꢏꢊꢓ ꢔꢈꢌꢉ ꢕ ꢈꢊ ꢖꢊ ꢑ  
ꢗ ꢉꢌ ꢘꢋꢄꢏꢏ ꢑꢊꢀꢀ ꢋꢑꢊ ꢙ ꢉ ꢀꢌ ꢊꢑ ꢀ  
SDAS060C − APRIL 1982 − REVISED DECEMBER 1994  
D OR N PACKAGE  
(TOP VIEW)  
Combines Decoder and 3-Bit Address  
Register  
Incorporates Two Enable Inputs to Simplify  
A
B
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Cascading  
Y0  
Y1  
Y2  
Y3  
Package Options Include Plastic  
Small-Outline (D) Packages and Standard  
Plastic (N) 300-mil DIPs  
C
CLK  
G2  
G1  
Y7  
11 Y4  
description  
10  
9
Y5  
Y6  
The SN74AS131A is  
a
3-line to 8-line  
GND  
decoder/demultiplexer with registers on the three  
address inputs. When the clock (CLK) input goes  
from low to high, the device acts as a decoder/  
demultiplexer and the address present at the select (A, B, and C) inputs is stored in the registers. Further  
address changes are ignored until the next rising transition of CLK. The output-enable (G1, G2) inputs control  
the state of the outputs independently of the select or CLK inputs. All of the outputs are high unless G1 is high  
and G2 is low. This device is ideally suited for implementing glitch-free decoders in strobed (stored-address)  
applications in bus-oriented systems.  
The SN74AS131A is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
ENABLE  
G1 G2  
SELECT  
CLK  
C
X
X
L
B
X
X
L
A
X
X
L
Y0  
H
H
L
Y1  
H
H
H
L
Y2  
H
H
H
H
L
Y3  
H
H
H
H
H
L
Y4  
H
H
H
H
H
H
L
Y5  
H
H
H
H
H
H
H
L
Y6  
H
H
H
H
H
H
H
H
L
Y7  
H
H
H
H
H
H
H
H
H
L
X
X
L
H
X
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
X
H
H
H
H
L
H
L
H
H
H
H
H
X
H
H
H
X
H
L or H  
Outputs corresponding to stored address = L; all others = H.  
ꢌꢥ  
Copyright 1994, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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