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SN74ALS843-1NT PDF预览

SN74ALS843-1NT

更新时间: 2024-11-29 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 540K
描述
ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24

SN74ALS843-1NT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:not_compliant
风险等级:5.31其他特性:WITH CLEAR AND PRESET; POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; IOL @ VCC = 4.75V
系列:ALSJESD-30 代码:R-PDIP-T24
长度:31.64 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
位数:9功能数量:1
端口数量:2端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):67 mA
传播延迟(tpd):26 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74ALS843-1NT 数据手册

 浏览型号SN74ALS843-1NT的Datasheet PDF文件第2页浏览型号SN74ALS843-1NT的Datasheet PDF文件第3页浏览型号SN74ALS843-1NT的Datasheet PDF文件第4页浏览型号SN74ALS843-1NT的Datasheet PDF文件第5页浏览型号SN74ALS843-1NT的Datasheet PDF文件第6页浏览型号SN74ALS843-1NT的Datasheet PDF文件第7页 
SN74ALS843  
9-BIT BUS-INTERFACE D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SDAS232A – DECEMBER 1983 – REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
Provides Extra Bus-Driving Latches  
Necessary for Wider Address/Data Paths or  
Buses With Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 PRE  
13 LE  
Buffered Control Inputs to Reduce  
dc Loading Effects  
Power-Up High-Impedance State  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
9D 10  
CLR 11  
GND 12  
description  
This 9-bit bus-interface D-type latch features  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers,  
I/O ports, bidirectional bus drivers, and working registers.  
The nine latches are transparent D-type latches with noninverting data (D) inputs.  
Abufferedoutput-enable(OE)inputplacesthenineoutputsineitheranormallogicstate(highorlowlogiclevels)  
or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operation of the latches. Previously stored data can be retained or new data can  
be entered while the outputs are off.  
The SN74ALS843 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE  
L
LE  
X
D
X
X
L
H
L
H
L
L
X
H
H
L
H
H
L
L
H
H
L
H
X
X
H
H
H
L
Q
0
X
X
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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