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SN74ALS843NT

更新时间: 2024-11-28 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 93K
描述
9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALS843NT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, PLASTIC, DIP-24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.9
Is Samacsys:N其他特性:WITH CLEAR AND PRESET
系列:ALSJESD-30 代码:R-PDIP-T24
JESD-609代码:e4长度:31.64 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:9
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):67 mA
传播延迟(tpd):26 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74ALS843NT 数据手册

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SN74ALS843  
9-BIT BUS-INTERFACE D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SDAS232A – DECEMBER 1983 – REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
Provides Extra Bus-Driving Latches  
Necessary for Wider Address/Data Paths or  
Buses With Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 PRE  
13 LE  
Buffered Control Inputs to Reduce  
dc Loading Effects  
Power-Up High-Impedance State  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
9D 10  
CLR 11  
GND 12  
description  
This 9-bit bus-interface D-type latch features  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers,  
I/O ports, bidirectional bus drivers, and working registers.  
The nine latches are transparent D-type latches with noninverting data (D) inputs.  
Abufferedoutput-enable(OE)inputplacesthenineoutputsineitheranormallogicstate(highorlowlogiclevels)  
or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operation of the latches. Previously stored data can be retained or new data can  
be entered while the outputs are off.  
The SN74ALS843 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE  
L
LE  
X
D
X
X
L
H
L
H
L
L
X
H
H
L
H
H
L
L
H
H
L
H
X
X
H
H
H
L
Q
0
X
X
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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