5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 计数器> SN74ALS568AFN
SN74ALS568AFN PDF预览

SN74ALS568AFN

更新时间： 2024-11-02 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 计数器输出元件
页数 文件大小 规格书
20页 608K
描述
IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,LDCC,20PIN,PLASTIC

阅读下载

中文翻译

获取价格

SN74ALS568AFN 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：QCCJ, LDCC20,.4SQReach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N计数方向：BIDIRECTIONAL
JESD-30 代码：S-PQCC-J20负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER工作模式：SYNCHRONOUS
功能数量：1端子数量：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified子类别：Counters
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

SN74ALS568AFN 数据手册

 浏览型号SN74ALS568AFN的Datasheet PDF文件第2页浏览型号SN74ALS568AFN的Datasheet PDF文件第3页浏览型号SN74ALS568AFN的Datasheet PDF文件第4页浏览型号SN74ALS568AFN的Datasheet PDF文件第5页浏览型号SN74ALS568AFN的Datasheet PDF文件第6页浏览型号SN74ALS568AFN的Datasheet PDF文件第7页 
SN54ALS569A, SN74ALS568A, SN74ALS569A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS  
WITH 3-STATE OUTPUTS  
SDAS229A – APRIL 1982 – REVISED JANUARY 1995  
SN54ALS569A . . . J PACKAGE  
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE  
(TOP VIEW)  
• 3-State Q Outputs Drive Bus Lines Directly  
• Counter Operation Independent of 3-State  
Output  
• Fully Synchronous Clear, Count, and Load  
• Asynchronous Clear Is Also Provided  
• Fully Cascadable  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
U/D  
CLK  
A
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
RCO  
CCO  
OE  
B
C
D
Q
A
Q
B
ENP  
ACLR  
SCLR  
GND  
Q
C
Q
D
12 ENT  
description  
11  
LOAD  
The SN74ALS568A decade counter and  
′ALS569A binary counters are programmable,  
count up or down, and offer both synchronous and  
asynchronous clearing. All synchronous functions  
are executed on the positive-going edge of the  
clock (CLK) input.  
SN54ALS569A . . . FK PACKAGE  
(TOP VIEW)  
The clear function is initiated by applying a low  
level to either asynchronous clear (ACLR) or  
synchronousclear(SCLR). Asynchronous(direct)  
clearing overrides all other functions of the device,  
while synchronous clearing overrides only the  
other synchronous functions. Data is loaded from  
the A, B, C, and D inputs by holding load (LOAD)  
low during a positive-going clock transition. The  
counting function is enabled only when enable P  
(ENP) and enable T (ENT) are low and ACLR,  
SCLR, and LOAD are high. The up/down (U/D)  
input controls the direction of the count. These  
counters count up when U/D is high and count  
down when U/D is low.  
3
2
1
20 19  
18  
CCO  
OE  
B
C
4
5
6
7
8
17  
16  
15  
14  
Q
D
A
Q
B
ENP  
ACLR  
Q
C
9 10 11 12 13  
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level  
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output  
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum  
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to  
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);  
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.  
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.  
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active  
until the clock returns to the low level.  
The SN54ALS569A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

中文翻译

下载PDF

与SN74ALS568AFN相关器件

型号 品牌 获取价格 描述 数据表
SN74ALS568AFN-00 TI

获取价格

 		ALS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PQCC20
SN74ALS568AJ4 TI

获取价格

 		IC IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,CERAMIC, Counter
SN74ALS568AJP4 TI

获取价格

 		IC IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,CERAMIC, Counter
SN74ALS568AN TI

获取价格

 		SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS
SN74ALS568AN1 TI

获取价格

 		IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,PLASTIC
SN74ALS568AN-10 TI

获取价格

 		ALS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP20
SN74ALS568ANP1 TI

获取价格

 		IC IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,PLASTIC, Counter
SN74ALS568ANP3 TI

获取价格

 		IC IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,PLASTIC, Counter
SN74ALS568J TI

获取价格

 		IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,CERAMIC
SN74ALS568J4 TI

获取价格

 		IC IC,COUNTER,UP/DOWN,DECADE,ALS-TTL,DIP,20PIN,CERAMIC, Counter

与SN74ALS568AFN相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证