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SN74ALS2238FN

更新时间： 2024-11-24 02:58:31
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
11页 178K
描述
32 X 9 X 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

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SN74ALS2238FN 数据手册

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SDAS182 − APRIL 1990  
N PACKAGE  
(TOP VIEW)  
D Independent Asychronous Inputs and  
Outputs  
D Bidirectional  
RSTA  
DAF  
A0  
A1  
A2  
GND  
A3  
A4  
RSTB  
DBF  
B0  
B1  
B2  
GND  
B3  
B4  
B5  
B6  
1
40  
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38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
D 32 Words by 9 Bits  
2
D Programmable Depth  
D Data Rates from 0 to 40 MHz  
D Fall-Through Time . . . 22 ns Typ  
D 3-State Outputs  
3
4
5
6
7
8
description  
A5  
A6  
GND  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
This 576-bit memory uses advanced low-power  
Schottky IMPACT-Xtechnology and features  
high speed and fast fall-through times. It consists  
of two FIFOs organized as 32 words by 9 bits  
each.  
GND  
V
V
CC  
CC  
A7  
A8  
B7  
B8  
LDCKA  
FULLA  
UNCKB  
EMPTYB  
SAB  
LDCKB  
FULLB  
UNCKA  
EMPTYA  
SBA  
A FIFO memory is a storage device that allows  
data to be written into and read from its array at  
independent data rates. These FIFOs are  
designed to process data at rates from 0 to 40  
MHz in a bit-parallel format, word by word.  
GAB  
GBA  
The SN74ALS2238 consists of bus-transceiver  
circuits, two 32 × 9 FIFOs, and control circuitry  
arranged for multiplexed transmission of data  
directly from the data bus or from the internal FIFO  
memories. Enables GAB and GBA are provided to  
control the transceiver functions. The SAB and  
SBA control pins are provided to select whether  
real-time or stored data is transferred. The  
circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer  
during the transition between stored and real-time  
data. A low level selects real-time data and a high  
selects stored data. Eight fundamental  
bus-management functions can be performed as  
shown in Figure 1.  
FN PACKAGE  
(TOP VIEW)  
6
5
4
3
2
1 44 43 42 41 40  
39  
B2  
GND  
GND  
7
8
9
V
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CC  
V
A3  
A4  
A5  
A6  
CC  
B3  
B4  
B5  
B6  
10  
11  
12  
13  
14  
15  
GND  
GND  
V
CC  
Data on the A or B data bus, or both, is written into  
the FIFOs on a low-to-high transition at the load  
clock (LDCKA or LDCKB) input and is read out on  
a low-to-high transition at the unload clock  
(UNCKA or UNCKB) input. The memory is full  
when the number of words clocked in exceeds, by  
the defined depth, the number of words clocked  
out.  
V
A7  
CC  
B7  
B8  
A8 16  
LDCKA  
17  
18 19 20 21 22 23 24 25 26 27 28  
When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is  
empty, UNCK signals have no effect.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IMPACT-X is a trademark of Texas Instruments Incorporated.  
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Copyright 1990, Texas Instruments Incorporated  
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

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