5秒后页面跳转
捷配首页

Datasheet > SN74ALS2238FN
SN74ALS2238FN PDF预览

SN74ALS2238FN

更新时间： 2024-09-27 02:58:31
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
11页 178K
描述
32 X 9 X 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

阅读下载

中文翻译

获取价格

SN74ALS2238FN 数据手册

 浏览型号SN74ALS2238FN的Datasheet PDF文件第2页浏览型号SN74ALS2238FN的Datasheet PDF文件第3页浏览型号SN74ALS2238FN的Datasheet PDF文件第4页浏览型号SN74ALS2238FN的Datasheet PDF文件第5页浏览型号SN74ALS2238FN的Datasheet PDF文件第6页浏览型号SN74ALS2238FN的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀꢆ ꢆꢇ ꢈ  
ꢘ
ꢇ
ꢆ × ꢉ ×  
ꢆ
ꢄ
ꢀ
ꢊ
ꢁ
ꢋ
ꢌ
ꢍ
ꢎ
ꢁ
ꢎ
ꢏ
ꢀ
ꢐ
ꢑ
ꢒ
ꢑ
ꢍ
ꢓ
ꢋ
ꢔ
ꢑ
ꢎ
ꢁ
ꢄ
ꢅ
ꢕ
ꢑ
ꢍ
ꢀ
ꢔ
ꢖ
ꢑ
ꢁ
ꢗ
ꢕ
ꢑ
ꢍ
ꢀ
ꢔ
ꢖ
ꢎ
ꢏ
ꢔ
ꢓ
ꢘ
ꢎ
ꢍ
ꢊ
SDAS182 − APRIL 1990  
N PACKAGE  
(TOP VIEW)  
D Independent Asychronous Inputs and  
Outputs  
D Bidirectional  
RSTA  
DAF  
A0  
A1  
A2  
GND  
A3  
A4  
RSTB  
DBF  
B0  
B1  
B2  
GND  
B3  
B4  
B5  
B6  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
D 32 Words by 9 Bits  
2
D Programmable Depth  
D Data Rates from 0 to 40 MHz  
D Fall-Through Time . . . 22 ns Typ  
D 3-State Outputs  
3
4
5
6
7
8
description  
A5  
A6  
GND  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
This 576-bit memory uses advanced low-power  
Schottky IMPACT-Xtechnology and features  
high speed and fast fall-through times. It consists  
of two FIFOs organized as 32 words by 9 bits  
each.  
GND  
V
V
CC  
CC  
A7  
A8  
B7  
B8  
LDCKA  
FULLA  
UNCKB  
EMPTYB  
SAB  
LDCKB  
FULLB  
UNCKA  
EMPTYA  
SBA  
A FIFO memory is a storage device that allows  
data to be written into and read from its array at  
independent data rates. These FIFOs are  
designed to process data at rates from 0 to 40  
MHz in a bit-parallel format, word by word.  
GAB  
GBA  
The SN74ALS2238 consists of bus-transceiver  
circuits, two 32 × 9 FIFOs, and control circuitry  
arranged for multiplexed transmission of data  
directly from the data bus or from the internal FIFO  
memories. Enables GAB and GBA are provided to  
control the transceiver functions. The SAB and  
SBA control pins are provided to select whether  
real-time or stored data is transferred. The  
circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer  
during the transition between stored and real-time  
data. A low level selects real-time data and a high  
selects stored data. Eight fundamental  
bus-management functions can be performed as  
shown in Figure 1.  
FN PACKAGE  
(TOP VIEW)  
6
5
4
3
2
1 44 43 42 41 40  
39  
B2  
GND  
GND  
7
8
9
V
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CC  
V
A3  
A4  
A5  
A6  
CC  
B3  
B4  
B5  
B6  
10  
11  
12  
13  
14  
15  
GND  
GND  
V
CC  
Data on the A or B data bus, or both, is written into  
the FIFOs on a low-to-high transition at the load  
clock (LDCKA or LDCKB) input and is read out on  
a low-to-high transition at the unload clock  
(UNCKA or UNCKB) input. The memory is full  
when the number of words clocked in exceeds, by  
the defined depth, the number of words clocked  
out.  
V
A7  
CC  
B7  
B8  
A8 16  
LDCKA  
17  
18 19 20 21 22 23 24 25 26 27 28  
When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is  
empty, UNCK signals have no effect.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IMPACT-X is a trademark of Texas Instruments Incorporated.  
ꢙ
ꢙ
ꢍ
ꢎ
ꢩ
ꢒ
ꢤ
ꢏ
ꢋ
ꢢ
ꢔ
ꢣ
ꢑ
ꢝ
ꢎ
ꢛ
ꢁ
ꢜ
ꢒ
ꢄ
ꢔ
ꢄ
ꢚ
ꢛ
ꢥ
ꢜ
ꢝ
ꢣ
ꢞ
ꢟ
ꢠ
ꢠ
ꢡ
ꢡ
ꢚ
ꢚ
ꢝ
ꢝ
ꢛ
ꢛ
ꢚ
ꢢ
ꢢ
ꢦ
ꢣ
ꢤ
ꢞ
ꢞ
ꢥ
ꢥ
ꢛ
ꢡ
ꢠ
ꢟ
ꢢ
ꢢ
ꢝ
ꢜ
ꢦ
ꢔꢥ  
ꢤ
ꢧ
ꢢ
ꢨ
ꢚ
ꢣ
ꢠ
ꢢ
ꢡ
ꢚ
ꢡ
ꢝ
ꢞ
ꢛ
ꢤ
ꢩ
ꢠ
ꢛ
ꢡ
ꢡ
ꢥ
ꢢ
ꢪ
Copyright 1990, Texas Instruments Incorporated  
ꢞ
ꢝ
ꢣ
ꢡ
ꢝ
ꢞ
ꢟ
ꢡ
ꢝ
ꢢ
ꢦ
ꢚ
ꢜ
ꢚ
ꢣ
ꢥ
ꢞ
ꢡ
ꢫ
ꢡ
ꢥ
ꢞ
ꢝ
ꢜ
ꢬ
ꢠ
ꢑ
ꢛ
ꢟ
ꢥ
ꢢ
ꢡ
ꢠ
ꢛ
ꢩ
ꢠ
ꢞ
ꢩ
ꢭ
ꢠ
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢞ
ꢞ
ꢠ
ꢛ
ꢡ
ꢮ
ꢪ
ꢙ
ꢞ
ꢝ
ꢩ
ꢤ
ꢣ
ꢡ
ꢚ
ꢝ
ꢛ
ꢦ
ꢞ
ꢝ
ꢣ
ꢥ
ꢢ
ꢢ
ꢚ
ꢛ
ꢯ
ꢩ
ꢝ
ꢥ
ꢢ
ꢛ
ꢝ
ꢡ
ꢛ
ꢥ
ꢣ
ꢥ
ꢢ
ꢢ
ꢠ
ꢞ
ꢚ
ꢨ
ꢮ
ꢚ
ꢛ
ꢣ
ꢨ
ꢤ
ꢩ
ꢥ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

中文翻译

下载PDF

与SN74ALS2238FN相关器件

型号 品牌 获取价格 描述 数据表
SN74ALS2238FNR TI

获取价格

 		32 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70
SN74ALS2238N TI

获取价格

 		32 x 9 x 2 Asynchronous Bidirectional FIFO Memory 40-PDIP 0 to 70
SN74ALS2240 TI

获取价格

 		OCTAL BUFFER AND LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS
SN74ALS2240DW TI

获取价格

 		OCTAL BUFFER AND LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS
SN74ALS2240DW3 TI

获取价格

 		IC,BUFFER/DRIVER,DUAL,4-BIT,ALS-TTL,SOP,20PIN,PLASTIC
SN74ALS2240DWR TI

获取价格

 		ALS SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20
SN74ALS2240N TI

获取价格

 		OCTAL BUFFER AND LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS
SN74ALS2240N3 TI

获取价格

 		ALS SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDIP20
SN74ALS2240NP3 TI

获取价格

 		IC,BUFFER/DRIVER,DUAL,4-BIT,ALS-TTL,DIP,20PIN,PLASTIC
SN74ALS229AN TI

获取价格

 		16X5 OTHER FIFO, 33ns, PDIP20

与SN74ALS2238FN相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证