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SN74AHCT573NSRE4

更新时间： 2024-12-01 05:24:55
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德州仪器 - TI 锁存器输出元件
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17页 546K
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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AHCT573NSRE4 数据手册

 浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第2页浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第3页浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第4页浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第5页浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第6页浏览型号SN74AHCT573NSRE4的Datasheet PDF文件第7页 
SN54AHCT573, SN74AHCT573  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS243N – OCTOBER 1995 – REVISED JULY 2003  
SN54AHCT573 . . . J OR W PACKAGE  
SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
The ’AHCT573 devices are octal transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is low, the Q outputs are latched at the  
logic levels of the D inputs.  
GND  
SN54AHCT573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
To ensure the high-impedance state during power  
9 10 11 12 13  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT573N  
SN74AHCT573N  
Tube  
SN74AHCT573DW  
SN74AHCT573DWR  
SN74AHCT573NSR  
SN74AHCT573DBR  
SN74AHCT573PW  
SN74AHCT573PWR  
SOIC – DW  
AHCT573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT573  
HB573  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB573  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT573DGVR HB573  
SNJ54AHCT573J  
SNJ54AHCT573W  
SNJ54AHCT573FK  
SNJ54AHCT573J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT573W  
SNJ54AHCT573FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

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