ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢊ ꢎꢋꢁ ꢏꢐꢑ ꢏꢒ ꢀꢋ ꢑ ꢋꢓꢍ ꢎꢁ ꢒꢔ ꢈ ꢄꢑꢍ
SCLS342L − APRIL 1996 − REVISED JUNE 2005
D
D
D
D
D
Operating Range of 2 V to 5.5 V
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Max t of 6.5 ns at 5 V
pd
Low Power Consumption, 10-µA Max I
CC
− 1000-V Charged-Device Model (C101)
8-mA Output Drive at 5 V
Schmitt Trigger Action at All Inputs Makes
the Circuit Tolerant for Slower Input Rise
and Fall Time
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
A
B
V
Y
1
2
3
5
1
2
3
5
A
B
V
Y
CC
CC
1
2
3
5
4
A
B
V
Y
CC
4
GND
4
GND
GND
See mechanical drawings for dimensions.
description/ordering information
This device contains a single 2-input NOR gate that performs the Boolean function Y = A S B or Y = A + B in
positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74AHC1G02DBVR
SN74AHC1G02DBVT
SN74AHC1G02DCKR
SN74AHC1G02DCKT
SN74AHC1G02DRLR
SOT (SOT-23) − DBV
A02_
−40°C to 85°C
SOT (SC-70) − DCK
AB_
AB_
SOT (SOT-553) – DRL
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
L
L
H
logic diagram (positive logic)
1
2
4
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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