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SN74AHC139DGV PDF预览

SN74AHC139DGV

更新时间： 2024-11-03 23:09:39
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
15页 491K
描述
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

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SN74AHC139DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.53
系列：AHC输入调节：STANDARD
JESD-30 代码：R-PDSO-G16长度：4.4 mm
逻辑集成电路类型：OTHER DECODER/DRIVER功能数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：16.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
宽度：3.6 mmBase Number Matches：1

SN74AHC139DGV 数据手册

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SN54AHC139, SN74AHC139  
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS  
SCLS259K – DECEMBER 1995 – REVISED MARCH 2003  
Operating Range 2-V to 5.5-V V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
Designed Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Incorporate Two Enable Inputs to Simplify  
Cascading and/or Data Reception  
– 1000-V Charged-Device Model (C101)  
SN54AHC139 . . . J OR W PACKAGE  
SN74AHC139 . . . D, DB, DGV, N, NS  
OR PW PACKAGE  
SN74AHC139 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHC139 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
16  
1G  
1A  
V
CC  
15 2G  
1
2
3
4
5
6
7
8
16  
3
2
1 20 19  
18  
2A  
17 2B  
1B  
1Y0  
NC  
4
5
6
7
8
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
1A  
1B  
1Y0  
1Y1  
1Y2  
1Y3  
2G  
2A  
2B  
2Y0  
2Y1  
2Y2  
14  
13  
12  
11  
10  
9
1B  
2A  
16  
NC  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
2B  
15  
14  
2Y0  
2Y1  
1Y1  
1Y2  
2Y0  
2Y1  
2Y2  
2Y3  
9 10 11 12 13  
8
9
NC – No internal connection  
description/ordering information  
The’AHC139devicesaredual2-lineto4-linedecoders/demultiplexersdesignedfor2-Vto5.5-VV operation.  
CC  
These devices are designed to be used in high-performance memory-decoding or data-routing applications  
requiring very short propagation delay times. In high-performance memory systems, these decoders can be  
used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable  
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical  
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHC139RGYR  
SN74AHC139N  
HA139  
SN74AHC139N  
Tube  
SN74AHC139D  
SOIC – D  
AHC139  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC139DR  
SN74AHC139NSR  
SN74AHC139DBR  
SN74AHC139PW  
SN74AHC139PWR  
SN74AHC139DGVR  
SNJ54AHC139J  
–40°C to 85°C  
SOP – NS  
AHC139  
HA139  
SSOP – DB  
TSSOP – PW  
HA139  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HA139  
SNJ54AHC139J  
SNJ54AHC139W  
SNJ54AHC139FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC139W  
SNJ54AHC139FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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