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SN74AHC126DE4 PDF预览

SN74AHC126DE4

更新时间： 2024-11-03 22:20:19
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
18页 567K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SN74AHC126DE4 数据手册

 浏览型号SN74AHC126DE4的Datasheet PDF文件第2页浏览型号SN74AHC126DE4的Datasheet PDF文件第3页浏览型号SN74AHC126DE4的Datasheet PDF文件第4页浏览型号SN74AHC126DE4的Datasheet PDF文件第5页浏览型号SN74AHC126DE4的Datasheet PDF文件第6页浏览型号SN74AHC126DE4的Datasheet PDF文件第7页 
SN54AHC126, SN74AHC126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS257L – DECEMBER 1995 – REVISED JULY 2003  
SN54AHC126 . . . J OR W PACKAGE  
SN74AHC126 . . . D, DB, DGV, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Operating Range 2-V to 5.5-V V  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
description/ordering information  
4A  
4Y  
3OE  
3A  
3Y  
The ’AHC126 devices are quadruple bus buffer  
gates featuring independent line drivers with  
3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low. When  
OE is high, the respective gate passes the data  
from the A input to its Y output.  
8
GND  
To ensure the high-impedance state during power  
up or power down, OE should be tied to GND  
through a pulldown resistor; the minimum value of  
the resistor is determined by the current-sourcing  
capability of the driver.  
SN54AHC126 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18 4A  
1Y  
NC  
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
2OE  
NC  
NC  
3OE  
2A  
9 10 11 12 13  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74AHC126N  
SN74AHC126N  
Tube  
SN74AHC126D  
AHC126  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC126DR  
SN74AHC126NSR  
SN74AHC126DBR  
SN74AHC126PW  
SN74AHC126PWR  
SN74AHC126DGVR  
SNJ54AHC126J  
SNJ54AHC126W  
SNJ54AHC126FK  
SOP – NS  
AHC126  
HA126  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HA126  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HA126  
SNJ54AHC126J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC126W  
SNJ54AHC126FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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SN74AHC126DE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC126DRE4 TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DR TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126D TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

与SN74AHC126DE4相关器件

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SN74AHC126DG4 TI

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SN74AHC126DGV TI

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SN74AHC126DGVR TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DGVRE4 TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DGVRG4 TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DR TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DRE4 TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126DRG4 TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126N TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC126NE4 TI

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 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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