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SN74ACT7808-40PAG PDF预览

SN74ACT7808-40PAG

更新时间： 2024-11-16 05:17:59
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
18页 293K
描述
2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY

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SN74ACT7808-40PAG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TFQFP, TQFP64,.47SQ针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.8
Is Samacsys：N最长访问时间：28 ns
最大时钟频率 (fCLK)：25 MHz周期时间：40 ns
JESD-30 代码：S-PQFP-G64JESD-609代码：e4
长度：10 mm内存密度：18432 bit
内存集成电路类型：OTHER FIFO内存宽度：9
湿度敏感等级：3功能数量：1
端子数量：64字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX9输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP64,.47SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

SN74ACT7808-40PAG 数据手册

 浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第2页浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第3页浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第4页浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第5页浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第6页浏览型号SN74ACT7808-40PAG的Datasheet PDF文件第7页 
SN74ACT7808  
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY  
SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001  
Load Clocks and Unload Clocks Can Be  
Asynchronous or Coincident  
Expansion Logic for Depth Cascading  
Empty, Full, and Half-Full Flags  
Fall-Through Time of 20 ns Typical  
Data Rates up to 50 MHz  
2048 Words by 9 Bits  
Low-Power Advanced CMOS Technology  
Fast Access Times of 15 ns With a 50-pF  
Load  
3-State Outputs  
Package Options Include 44-Pin Plastic  
Leaded Chip Carrier (FN), 64-Pin Thin Quad  
Flat (PM), and Reduced-Height 64-Pin Quad  
Flat (PAG) Packages  
Programmable Almost-Full/Almost-Empty  
Flag  
description  
A FIFO memory is a storage device that allows data to be written into and read from its array at independent  
data rates. The SN74ACT7808 is a 2048-word by 9-bit FIFO designed for high speed and fast access times.  
It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.  
Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a  
low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked  
in exceeds the number of words clocked out by 2048. When the memory is full, LDCK signals have no effect  
on the data residing in memory. When the memory is empty, UNCK signals have no effect.  
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and  
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the  
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF  
output is high when the FIFO contains 1024 or more words and is low when it contains 1023 or fewer words.  
The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset  
can be used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable  
(PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words.  
The AF/AE flag is low when the FIFO contains between (X + 1) and (2047 – Y) words.  
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF  
low, and EMPTY low. The Q outputs are not reset to any specific logic level.  
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.  
Itisimportanttonotethatthefirstworddoesnothavetobeunloaded. Dataoutputsarenoninvertingwithrespect  
to the data inputs and are in the high-impedance state when the output-enable (OE) input is low. OE does not  
affect the output flags.  
Cascading is easily accomplished in the word-width and word-depth directions. When not using the FIFO in  
depth expansion, cascade enable (CASEN) must be tied high.  
The FIFO must be reset upon power up.  
The SN74ACT7808 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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SN74ACT7808-40PAG 替代型号

型号 品牌 替代类型 描述 数据表
72V831L10PFG8 IDT

功能相似

 3.3 VOLT DUAL CMOS SyncFIFO

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SN74ACT7808-40PM TI

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 		2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7808-40PMR TI

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SN74ACT7808PAG TI

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 		2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7808PM TI

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 		2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7811 TI

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 		1024 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7811-15FN ROCHESTER

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 		1KX18 OTHER FIFO, 15ns, PQCC68, PLASTIC, LCC-68
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 		1KX18 OTHER FIFO, 15ns, PQCC68, PLASTIC, LCC-68
SN74ACT7811-15PN ROCHESTER

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