Datasheet > 存储 > FIFO> SN74ACT3631-20PCBR

SN74ACT3631-20PCBR

更新时间： 2024-11-15 13:13:47

品牌	Logo	应用领域
德州仪器 - TI		存储
页数	文件大小	规格书
26页	379K
描述
512X36 OTHER FIFO, 13ns, PQFP120, GREEN, PLASTIC, HLQFP-120

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SN74ACT3631-20PCBR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HLFQFP,	针数：	120
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.36
最长访问时间：	13 ns	其他特性：	MAILBOX
周期时间：	20 ns	JESD-30 代码：	S-PQFP-G120
长度：	14 mm	内存密度：	18432 bit
内存宽度：	36	功能数量：	1
端子数量：	120	字数：	512 words
字数代码：	512	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512X36	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.4 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

SN74ACT3631-20PCBR 数据手册

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SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Output-Ready and Almost-Empty Flags

Synchronized by CLKB

Clocked FIFO Buffering Data From Port A

to Port B

Low-Power 0.8-µm Advanced CMOS

Technology

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 11 ns

Programmable Almost-Full and

Almost-Empty Flags

Pin-to-Pin Compatible With the

SN74ACT3641 and SN74ACT3651

Microprocessor Interface Control Logic

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

Input-Ready and Almost-Full Flags

Synchronized by CLKA

description

The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies

up to 67 MHz and has read access times as fast as 11 ns. The 512 × 36 dual-port SRAM FIFO buffers data from

port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed

again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and

almost empty) to indicate when a selected number of words is stored in memory. Communication between each

port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail

has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is

possible in word depth.

The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset

values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.

The SN74ACT3631 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA007)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number

SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...26

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与SN74ACT3631-20PCBR相关器件

型号	品牌	获取价格	描述	数据表
SN74ACT3631-20PQ	TI	获取价格	512 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT3631-30PCB	TI	获取价格	512 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT3631-30PCBR	TI	获取价格	暂无描述
SN74ACT3631-30PQ	TI	获取价格	512 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT3631PCB	TI	获取价格	512 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT3631PQ	TI	获取价格	512 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT3632	TI	获取价格	512 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ACT3632-15PCBR	TI	获取价格	512X36 BI-DIRECTIONAL FIFO, 11ns, PQFP120, TQFP-120
SN74ACT3632-20PCB	TI	获取价格	512 x 36 x 2 bidirectional synchronous FIFO memory 120-HLQFP 0 to 70
SN74ACT3632-20PCBR	TI	获取价格	512X36 BI-DIRECTIONAL FIFO, 13ns, PQFP120, TQFP-120

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