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SN74ACT2236-20PAG PDF预览

SN74ACT2236-20PAG

更新时间: 2024-10-29 21:04:55
品牌 Logo 应用领域
德州仪器 - TI 先进先出芯片
页数 文件大小 规格书
14页 227K
描述
2KX9 BI-DIRECTIONAL FIFO, PQFP64

SN74ACT2236-20PAG 技术参数

生命周期:Obsolete包装说明:TFQFP,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.8
JESD-30 代码:S-PQFP-G64长度:10 mm
内存密度:18432 bit内存宽度:9
功能数量:1端子数量:64
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS组织:2KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.2 mm
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

SN74ACT2236-20PAG 数据手册

 浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第2页浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第3页浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第4页浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第5页浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第6页浏览型号SN74ACT2236-20PAG的Datasheet PDF文件第7页 
ꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢇꢈ ꢉ  
× ×  
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995  
D Independent Asynchronous Inputs and  
D Access Times of 25 ns With a 50-pF Load  
D Data Rates From 0 to 50 MHz  
Outputs  
D Low-Power Advanced CMOS Technology  
D Fall-Through Times of 23 ns Max  
D High Output Drive for Direct Bus Interface  
D 3-State Outputs  
D Bidirectional  
D 1024 Words by 9 Bits Each  
D Programmable Almost-Full/Almost-Empty  
D Available in 44-Pin PLCC (FN) Package  
Flag  
D Empty, Full, and Half-Full Flags  
FN PACKAGE  
(TOP VIEW)  
6
5
4
3
2 1 44 43 42 41 40  
B2  
B3  
B4  
V
B5  
B6  
B7  
B8  
GND  
AF/AEB  
HFB  
A3  
A4  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
8
V
9
CC  
A5  
10  
11  
12  
13  
14  
15  
16  
17  
CC  
A6  
A7  
A8  
GND  
AF/AEA  
HFA  
LDCKA  
18 19 20 21 22 23 24 25 26 27 28  
description  
A FIFO memory is a storage device that allows data to be written into and read from its array at independent  
data rates. The SN74ACT2236 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.  
It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit-parallel format.  
The SN74ACT2236 consists of bus-transceiver circuits, two 1024 × 9 FIFOs, and control circuitry arranged for  
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable OE and  
DIR inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are  
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates  
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.  
Figure 1 shows the five fundamental bus-management functions that can be performed with the SN74ACT2236.  
The SN74ACT2236 is characterized for operation from 0°C to 70°C.  
For more information on this device family, see the application report 1K 9 2 Asynchronous FIFOs  
SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories Designer’s Handbook,  
literature number SCAA012A.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢧ  
Copyright 1995, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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