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SN74ABT8996PW

更新时间： 2024-11-24 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管信息通信管理双倍数据速率
页数 文件大小 规格书
40页 565K
描述
10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS

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SN74ABT8996PW 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.79Is Samacsys：N
外部数据总线宽度：JESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
湿度敏感等级：1端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Other Microprocessor ICs
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

SN74ABT8996PW 数据手册

 浏览型号SN74ABT8996PW的Datasheet PDF文件第2页浏览型号SN74ABT8996PW的Datasheet PDF文件第3页浏览型号SN74ABT8996PW的Datasheet PDF文件第4页浏览型号SN74ABT8996PW的Datasheet PDF文件第5页浏览型号SN74ABT8996PW的Datasheet PDF文件第6页浏览型号SN74ABT8996PW的Datasheet PDF文件第7页 
SN54ABT8996, SN74ABT8996  
10-BIT ADDRESSABLE SCAN PORTS  
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS  
SCBS489C – AUGUST 1994 – REVISED APRIL 1999  
SN54ABT8996 . . . JT PACKAGE  
SN74ABT8996 . . . DW OR PW PACKAGE  
(TOP VIEW)  
Members of Texas Instruments Broad  
Family of Testability Products Supporting  
IEEE Std 1149.1-1990 (JTAG) Test Access  
Port (TAP) and Boundary-Scan Architecture  
A4  
A3  
A2  
A1  
A0  
A5  
A6  
A7  
A8  
A9  
V
CON  
STDI  
STCK  
STMS  
STDO  
STRST  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Extend Scan Access From Board Level to  
Higher Levels of System Integration  
2
3
Promote Reuse of Lower-Level  
(Chip/Board) Tests in System Environment  
4
5
BYP  
GND  
PTDO  
PTCK  
PTMS  
PTDI  
PTRST  
6
Switch-Based Architecture Allows Direct  
Connect of Primary TAP to Secondary TAP  
CC  
7
8
Primary TAP Is Multidrop for Minimal Use of  
Backplane Wiring Channels  
9
10  
11  
12  
Simple Addressing (Shadow) Protocol Is  
Received/Acknowledged on Primary TAP  
Shadow Protocols Can Occur in Any of  
Test-Logic-Reset, Run-Test/Idle, Pause-DR,  
and Pause-IR TAP States to Provide for  
Board-to-Board Test and Built-In Self-Test  
SN54ABT8996 . . . FK PACKAGE  
(TOP VIEW)  
10-Bit Address Space Provides for Up to  
1021 User-Specified Board Addresses  
4
3
2
1 28 27 26  
25  
Bypass (BYP) Pin Forces  
Primary-to-Secondary Connection Without  
Use of Shadow Protocols  
A1  
A0  
A8  
A9  
V
5
24  
23  
22  
6
BYP  
NC  
7
CC  
NC  
Connect (CON) Pin Provides Indication of  
Primary-to-Secondary Connection  
8
GND  
PTDO  
PTCK  
21 CON  
20 STDI  
9
10  
11  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
19  
STCK  
Support Backplane Interface at Primary and  
High Fanout at Secondary  
12 13 14 15 16 17 18  
Package Options Include Plastic Small-  
Outline (DW) and Thin Shrink Small-  
Outline (PW) Packages, Ceramic Chip  
Carriers (FK), and Ceramic DIPs (JT)  
NC – No internal connection  
description  
The ’ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TI ) SCOPE  
testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan  
to facilitate testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a  
boundary-scannable device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Standard  
1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.  
Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP  
signals to a set of secondary TAP signals – for example, to interface backplane TAP signals to a board-level  
TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and  
secondary TAPs are connected, only a moderate propagation delay is introduced – no storage/retiming  
elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...40

中文翻译

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SN74ABT8996PW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT8996PWLE TI

完全替代

 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVER
SN74ABT8996PWR TI

完全替代

 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceiver

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