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SN74ABT853PWG4 PDF预览

SN74ABT853PWG4

更新时间： 2024-11-21 15:52:03
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
21页 665K
描述
ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24

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SN74ABT853PWG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP24,.25
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.64
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G24
长度：7.8 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.064 A位数：8
功能数量：2端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：38 mA
Prop。Delay @ Nom-Sup：5.3 ns传播延迟（tpd）：5.3 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：4.4 mmBase Number Matches：1

SN74ABT853PWG4 数据手册

 浏览型号SN74ABT853PWG4的Datasheet PDF文件第2页浏览型号SN74ABT853PWG4的Datasheet PDF文件第3页浏览型号SN74ABT853PWG4的Datasheet PDF文件第4页浏览型号SN74ABT853PWG4的Datasheet PDF文件第5页浏览型号SN74ABT853PWG4的Datasheet PDF文件第6页浏览型号SN74ABT853PWG4的Datasheet PDF文件第7页 
SN54ABT853, SN74ABT853  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997  
SN54ABT853 . . . JT OR W PACKAGE  
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OEA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 5 V, T = 25°C  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
High-Impedance State During Power Up  
and Power Down  
ERR 10  
15 PARITY  
Parity-Error Flag With Parity  
Generator/Checker  
CLR  
GND  
OEB  
LE  
11  
12  
14  
13  
Latch for Storage of Parity-Error Flag  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
SN54ABT853 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
5
A3  
A4  
A5  
NC  
A6  
A7  
A8  
B3  
B4  
B5  
NC  
B6  
B7  
B8  
6
description  
24  
23  
22  
21  
20  
19  
7
The ’ABT853 8-bit to 9-bit parity transceivers are  
designedforcommunicationbetweendatabuses.  
When data is transmitted from the A bus to the  
B bus, a parity bit is generated. When data is  
transmitted from the B bus to the A bus with its  
corresponding parity bit, the open-collector  
parity-error (ERR) output indicates whether or not  
an error in the B data has occurred. The  
output-enable (OEA and OEB) inputs can be used  
to disable the device so that the buses are  
effectively isolated. The ’ABT853 transceivers  
provide true data at their outputs.  
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the  
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from  
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the  
designer more system diagnostic capability.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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