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SN74ABT8245DW PDF预览

SN74ABT8245DW

更新时间: 2024-11-16 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路测试光电二极管信息通信管理PC
页数 文件大小 规格书
25页 362K
描述
SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS

SN74ABT8245DW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SO-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.26Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:605063
Samacsys Pin Count:24Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOIC127P1030X265-24N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:ABT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BOUNDARY SCAN BUS TRANSCEIVER最大I(ol):0.064 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):38 mA
Prop。Delay @ Nom-Sup:5.8 ns传播延迟(tpd):5.1 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

SN74ABT8245DW 数据手册

 浏览型号SN74ABT8245DW的Datasheet PDF文件第2页浏览型号SN74ABT8245DW的Datasheet PDF文件第3页浏览型号SN74ABT8245DW的Datasheet PDF文件第4页浏览型号SN74ABT8245DW的Datasheet PDF文件第5页浏览型号SN74ABT8245DW的Datasheet PDF文件第6页浏览型号SN74ABT8245DW的Datasheet PDF文件第7页 
SN54ABT8245, SN74ABT8245  
SCAN TEST DEVICES  
WITH OCTAL BUS TRANSCEIVERS  
SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996  
SN54ABT8245 . . . JT PACKAGE  
SN74ABT8245 . . . DW PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port  
and Boundary-Scan Architecture  
1
24  
23  
22  
DIR  
B1  
B2  
OE  
A1  
A2  
2
Functionally Equivalent to ’F245 and  
’ABT245 in the Normal-Function Mode  
3
4
21 A3  
20 A4  
19 A5  
B3  
B4  
GND  
B5  
B6  
B7  
B8  
TDO  
TMS  
5
SCOPE Instruction Set:  
6
– IEEE Standard 1149.1-1990 Required  
Instructions, Optional INTEST, CLAMP,  
and HIGHZ  
– Parallel-Signature Analysis at Inputs  
With Masking Option  
7
18  
17  
16  
15  
14  
13  
V
CC  
A6  
8
A7  
9
A8  
10  
11  
12  
TDI  
TCK  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Even-Parity Opcodes  
SN54ABT8245 . . . FK PACKAGE  
(TOP VIEW)  
Two Boundary-Scan Cells per I/O for  
Greater Flexibility  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
4
3
2 1 28 27 26  
5
6
7
8
9
25  
24  
23  
22  
21  
20  
19  
A2  
A1  
A8  
Package Options Include Plastic  
Small-Outline Packages (DW), Ceramic  
Chip Carriers(FK), and Standard Ceramic  
DIPs (JT)  
TDI  
TCK  
NC  
OE  
NC  
DIR  
B1  
TMS  
TDO  
B8  
10  
11  
description  
B2  
12 13 14 15 16 17 18  
The ’ABT8245 scan test devices with octal bus  
transceivers are members of the Texas Instru-  
ments SCOPE  
testability integrated-circuit  
family. This family of devices supports IEEE  
Standard 1149.1-1990 boundary scan to facilitate  
testing of complex circuit-board assemblies. Scan  
access to the test circuitry is accomplished via the  
4-wire test access port (TAP) interface.  
NC – No internal connection  
In the normal mode, these devices are functionally equivalent to the ’F245 and ’ABT245 octal bus transceivers.  
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins  
or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the  
functional operation of the SCOPE octal bus transceivers.  
Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is  
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The  
output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ABT8245DW 替代型号

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SN74ABT8245DWRG4 TI

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