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SN65MLVD040RGZR PDF预览

SN65MLVD040RGZR

更新时间: 2024-01-02 09:59:48
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德州仪器 - TI /
页数 文件大小 规格书
29页 813K
描述
4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

SN65MLVD040RGZR 数据手册

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SN65MLVD040  
www.ti.com  
SLLS902 FEBRUARY 2010  
4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS  
Check for Samples: SN65MLVD040  
1
FEATURES  
APPLICATIONS  
Parallel Multipoint Data and Clock  
Transmission Via Backplanes and Cables  
Low-Power High-Speed Short-Reach  
Alternative to TIA/EIA-485  
2
Low-Voltage Differential 30-to 55-Line  
Drivers and Receivers for Signaling Rates(1) Up  
to 250 Mbps; Clock Frequencies Up to  
125 MHz  
Cellular Base Stations  
Central-Office Switches  
Network Switches and Routers(1)  
Meets or Exceeds the M-LVDS Standard  
TIA/EIA-899 for Multipoint Data Interchange  
Controlled Driver Output Voltage Transition  
Times for Improved Signal Quality  
LOGIC DIAGRAM (POSITIVE LOGIC)  
SN65MLVD040  
–1 V to 3.4 V Common-Mode Voltage Range  
Allows Data Transfer With 2 V of Ground Noise  
Channel 1  
1DE  
1A  
Bus Pins High Impedance When Driver  
Disabled or VCC 1.5 V  
1D  
1B  
1FSEN  
Independent Enables for each Driver and  
Receiver  
1R  
1RE  
PDN  
Enhanced ESD Protection: 7 kV HBM on all  
Pins  
2DE - 4E  
3
48 pin 7 X 7 QFN (RGZ)  
2D - 4D  
3
M-LVDS Bus Power Up/Down Glitch Free  
2A - 4A  
2FSEN –  
Channels 2 - 4  
3
4FSEN  
2B - 4B  
2R - 4R  
3
3
2RE – 4RE  
(1) The signaling rate of a line, is the number of voltage  
transitions that are made per second expressed in the units  
bps (bits per second).  
DESCRIPTION  
The SN65MLVD040 provides four half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage  
Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at  
signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting  
loads as low as 30-and incorporates controlled transition times to allow for stubs off of the backplane  
transmission line.  
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have  
thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2  
receivers implement a failsafe by using an offset threshold. The xFSEN pins is used to select the Type-1 and  
Type-2 receiver for each of the channels. In addition, the driver rise and fall times are between 1 ns and 2 ns,  
complying with the M-LVDS standard to provide operation at 250 Mbps while also accommodating stubs on the  
bus. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current  
surges. The M-LVDS standard allows for 32 nodes on the bus providing a high-speed replacement for RS-485  
where lower common-mode can be tolerated or when higher signaling rates are needed.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  

SN65MLVD040RGZR 替代型号

型号 品牌 替代类型 描述 数据表
SN65MLVD040RGZT TI

完全替代

4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

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