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SN65MLVD080DGGRG4 PDF预览

SN65MLVD080DGGRG4

更新时间： 2024-11-24 04:31:19
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
28页 527K
描述
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

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中文翻译

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SN65MLVD080DGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP64,.32,20针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.32
Is Samacsys：N差分输出：YES
驱动器位数：8高电平输入电流最大值：0.00001 A
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-899; TIA-899JESD-30 代码：R-PDSO-G64
JESD-609代码：e4长度：17 mm
湿度敏感等级：2功能数量：8
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.48 V
输出特性：DIFFERENTIAL最大输出低电流：0.008 A
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP64,.32,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：8座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：180 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：2.4 ns宽度：6.1 mm
Base Number Matches：1

SN65MLVD080DGGRG4 数据手册

 浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第2页浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第3页浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第4页浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第5页浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第6页浏览型号SN65MLVD080DGGRG4的Datasheet PDF文件第7页 
SN65MLVD080  
SN65MLVD082  
www.ti.com  
SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005  
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS  
The M-LVDS standard defines two types of receivers,  
designated as Type-1 and Type-2. Type-1 receivers  
(SN65MLVD080) have thresholds centered about  
zero with 25 mV of hysteresis to prevent output  
oscillations with loss of input; Type-2 receivers  
(SN65MLVD082) implement a failsafe by using an  
offset threshold. In addition, the driver rise and fall  
times are between 1 and 2.0 ns, complying with the  
M-LVDS standard to provide operation at 250 Mbps  
while also accommodating stubs on the bus. Receiver  
outputs are slew rate controlled to reduce EMI and  
crosstalk effects associated with large current surges.  
The M-LVDS standard allows for 32 nodes on the bus  
providing a high-speed replacement for RS-485  
where lower common-mode can be tolerated or when  
higher signaling rates are needed.  
FEATURES  
•
Low-Voltage Differential 30-Ω to 55-Ω Line  
Drivers and Receivers for Signaling Rates  
Up to 250 Mbps; Clock Frequencies Up to  
125 MHz  
(1)  
•
•
•
Meets or Exceeds the M-LVDS Standard  
TIA/EIA-899 for Multipoint Data Interchange  
Controlled Driver Output Voltage Transition  
Times for Improved Signal Quality  
–1 V to 3.4 V Common-Mode Voltage Range  
Allows Data Transfer With 2 V of Ground  
Noise  
•
Bus Pins High Impedance When Driver  
Disabled or VCC ≤ 1.5 V  
The driver logic inputs and the receiver logic outputs  
are on separate pins rather than tied together as in  
some transceiver designs. The drivers have separate  
enables (DE) and the receivers are enabled globally  
through (RE). This arrangement of separate logic  
inputs, logic outputs, and enable pins allows for a  
listen-while-talking operation. The devices are  
characterized for operation from –40°C to 85°C.  
•
•
•
•
Independent Enables for each Driver  
Bus Pin ESD Protection Exceeds 8 kV  
Packaged in 64-Pin TSSOP (DGG)  
M-LVDS Bus Power Up/Down Glitch Free  
APPLICATIONS  
•
Parallel Multipoint Data and Clock  
Transmission Via Backplanes and Cables  
Low-Power High-Speed Short-Reach  
Alternative to TIA/EIA-485  
Cellular Base Stations  
Central-Office Switches  
Network Switches and Routers  
LOGIC DIAGRAM (POSITIVE LOGIC)  
•
SN65MLVD080, SN65MLVD082  
Channel 1  
1DE  
•
•
•
1A  
1D  
1B  
1R  
RE  
DESCRIPTION  
The SN65MLVD080 and SN65MLVD082 provide  
eight half-duplex transceivers for transmitting and  
receiving Multipoint-Low-Voltage Differential Signals  
in full compliance with the TIA/EIA-899 (M-LVDS)  
standard, which are optimized to operate at signaling  
rates up to 250 Mbps. The driver outputs have been  
designed to support multipoint buses presenting  
loads as low as 30-Ω and incorporates controlled  
transition times to allow for stubs off of the backbone  
transmission line.  
7
2DE - 8DE  
2A - 8A  
2B - 8B  
7
2D - 8D  
2R - 8R  
Channels 2 - 8  
7
(1) The signaling rate of a line, is the number of voltage  
transitions that are made per second expressed in the units  
bps (bits per second).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN65MLVD080DGGRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65MLVD080DGGR TI

完全替代

 8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
SN65MLVD080DGG TI

完全替代

 8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS
SN65MLVD080DGGG4 TI

类似代替

 8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

与SN65MLVD080DGGRG4相关器件

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SN65MLVD082 TI

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 		8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS
SN65MLVD082DGG TI

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 		8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS
SN65MLVD082DGGG4 TI

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 		8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
SN65MLVD082DGGR TI

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 		8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
SN65MLVD082DGGRG4 TI

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 		8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
SN65MLVD128 TI

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 		1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER
SN65MLVD128DGG TI

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 		1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER
SN65MLVD128DGGG4 TI

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 		LINE TRANSCEIVER, PDSO48, GREEN, PLASTIC, TSSOP-48
SN65MLVD128DGGR TI

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 		1:8 LVTTL 到 M-LVDS 中继器 | DGG | 48 | -40 to 85
SN65MLVD128DGGRG4 TI

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 		LINE TRANSCEIVER, PDSO48, GREEN, PLASTIC, TSSOP-48

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