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SN65512BDWR PDF预览

SN65512BDWR

更新时间: 2024-11-05 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 显示器驱动
页数 文件大小 规格书
7页 111K
描述
VACUUM FLUOR DISPLAY DRIVER, PDSO20

SN65512BDWR 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N数据输入模式:SERIAL
显示模式:DOT MATRIX输入特性:STANDARD
接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVERJESD-30 代码:R-PDSO-G20
长度:12.8 mm复用显示功能:NO
功能数量:1区段数:12
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:TOTEM-POLE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:2.65 mm最大压摆率:6 mA
最大供电电压:15 V最小供电电压:5 V
标称供电电压:12 V电源电压1-最大:60 V
电源电压1-分钟:电源电压1-Nom:30 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mm最小 fmax:1 MHz
Base Number Matches:1

SN65512BDWR 数据手册

 浏览型号SN65512BDWR的Datasheet PDF文件第2页浏览型号SN65512BDWR的Datasheet PDF文件第3页浏览型号SN65512BDWR的Datasheet PDF文件第4页浏览型号SN65512BDWR的Datasheet PDF文件第5页浏览型号SN65512BDWR的Datasheet PDF文件第6页浏览型号SN65512BDWR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢀꢁ ꢉꢃ ꢃꢄ ꢅꢆ  
ꢊꢋꢆꢌ ꢌꢍꢈ ꢎ ꢏꢌ ꢐꢑ ꢒꢀꢆꢒ ꢁꢓ ꢈꢔ ꢕꢀꢖꢏ ꢋꢗꢈ ꢔꢑ ꢕ ꢊꢒ ꢑ ꢀ  
SLDS054 − D3516, MAY 1990  
DW OR N PACKAGE  
(TOP VIEW)  
Each Device Drives 12 Lines  
60-V Output Voltage Swing Capability  
25-mA Output Source Current Capability  
High-Speed Serially-Shifted Data Input  
TTL-Compatible Inputs  
Q11  
Q12  
STROBE  
Q10  
Q9  
Q8  
Q7  
V
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
SERIAL OUT  
DATA IN  
Latches on All Driver Outputs  
CC2  
V
15 GND  
CC1  
description  
14  
13  
12  
11  
CLOCK  
Q6  
Q5  
Q4  
Q3  
The SN65512C and SN75512C are monolithic  
LATCH ENABLE  
BIDFET integrated circuits designed to drive a  
Q1  
Q2  
dot matrix or segmented vacuum fluorescent  
display.  
All device inputs are diode-clamped pnp inputs  
and assume a high logic level when open  
circuited. The nominal input threshold is 1.5 V.  
Outputs are totem-pole structures formed by an  
npn emitter follower and double-diffused MOS  
(DMOS) transistors.  
logic symbol  
TTL/VAC  
FLUOR DISPLAY  
8
3
LATCH ENABLE  
STROBE  
The device consists of a 12-bit shift register,  
12 latches, and 12 output AND gates. Serial data  
is entered into the shift register on the low-to-high  
transition of CLOCK. When high, LATCH ENABLE  
transfers the shift register contents to the outputs  
of the 12 latches. The active-low STROBE input  
enables all Q outputs. Serial data output from the  
shift register can be used to cascade shift  
registers. This output is not affected by LATCH  
ENABLE or STROBE.  
SRG12  
C1/  
7
5
CLOCK  
DATA IN  
9
10  
11  
12  
13  
14  
17  
18  
19  
20  
1
2D  
2D  
2D  
2D  
2D  
2D  
2D  
2D  
2D  
2D  
2D  
2D  
3
3
3
3
3
3
3
3
3
3
3
3
Q1  
Q2  
Q3  
Q4  
The SN65512C is characterized for operation  
from 40°C to 85°C. The SN75512C is  
characterized for operation from 0°C to 70°C.  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Q11  
2
Q12  
4
SERIAL OUT  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
BIDFET − Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.  
ꢓꢤ  
Copyright 1990, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
4−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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