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SN54LS221 PDF预览

SN54LS221

更新时间: 2024-11-18 23:03:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器输入元件
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7页 196K
描述
DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

SN54LS221 数据手册

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SN54/74LS221  
DUAL MONOSTABLE  
MULTIVIBRATORS  
WITH SCHMITT-TRIGGER INPUTS  
DUAL MONOSTABLE  
MULTIVIBRATORS  
WITH SCHMITT-TRIGGER INPUTS  
Each multivibrator of the LS221 features a negative-transition-triggered  
input and a positive-transition-triggered input either of which can be used as  
an inhibit input.  
Pulse triggering occurs at a voltage level and is not related to the transition  
time of the input pulse. Schmitt-trigger input circuitry for B input allows  
jitter-free triggering for inputs as slow as 1 volt/second, providing the circuit  
LOW POWER SCHOTTKY  
with excellent noise immunity. A high immunity to V  
by internal latching circuitry.  
noise is also provided  
CC  
Once triggered, the outputs are independent of further transitions of the  
inputs and are a function of the timing components. The output pulses can be  
terminated by the overriding clear. Input pulse width may be of any duration  
relative to the output pulse width. Output pulse width may be varied from 35  
nanoseconds to a maximum of 70 s by choosing appropriate timing  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
components. With R  
= 2.0 kand C  
= 0, a typical output pulse of 30  
ext  
ext  
nanoseconds is achieved. Output rise and fall times are independent of pulse  
length.  
Pulse width stability is achieved through internal compensation and is  
N SUFFIX  
PLASTIC  
CASE 648-08  
virtually independent of V  
and temperature. In most applications, pulse  
CC  
stability will only be limited by the accuracy of external timing components.  
Jitter-freeoperationismaintainedoverthefulltemperatureandV ranges  
16  
CC  
1
for greater than six decades of timing capacitance (10 pF to 10 µF), and  
greater than one decade of timing resistance (2.0 to 70 kfor the  
SN54LS221, and 2.0 to 100 kfor the SN74LS221). Pulse width is defined  
D SUFFIX  
SOIC  
CASE 751B-03  
bytherelationship:t (out)=C  
R
ln2.00.7C  
R
;wheret isinns  
W
w
ext ext  
ext ext  
if C  
ext  
is in pF and R is in k. If pulse cutoff is not critical, capacitance up  
16  
ext  
1
to 1000 µF and resistance as low as 1.4 kmay be used. The range of  
jitter-free pulse widths is extended if V is 5.0 V and 25°C temperature.  
CC  
SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot  
Overriding Clear Terminates Output Pulse  
Pin Out is Identical to SN54/74LS123  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
FUNCTION TABLE  
(EACH MONOSTABLE)  
(TOP VIEW)  
INPUTS  
OUTPUTS  
CLEAR  
A
B
Q
Q
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
H
H
*
L
*See operational notes — Pulse Trigger Modes  
TYPICAL  
POWER  
DISSIPATION  
23 mW  
MAXIMUM  
TYPE  
OUTPUT PULSE  
LENGTH  
49 s  
positive logic: Low input to clear resets Q low and  
positive logic: Q high regardless of dc levels at A  
positive logic: or B inputs.  
SN54LS221  
SN74LS221  
23 mW  
70 s  
FAST AND LS TTL DATA  
5-380  

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