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SN54HC563WR PDF预览

SN54HC563WR

更新时间： 2024-11-02 20:50:55
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
7页 109K
描述
HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, FP-20

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SN54HC563WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknown风险等级：5.76
其他特性：BROADSIDE VERSION OF 533系列：HC/UH
JESD-30 代码：R-GDFP-F20长度：13.09 mm
负载电容（CL）：150 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：335 ns认证状态：Not Qualified
座面最大高度：2.54 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.92 mmBase Number Matches：1

SN54HC563WR 数据手册

 浏览型号SN54HC563WR的Datasheet PDF文件第2页浏览型号SN54HC563WR的Datasheet PDF文件第3页浏览型号SN54HC563WR的Datasheet PDF文件第4页浏览型号SN54HC563WR的Datasheet PDF文件第5页浏览型号SN54HC563WR的Datasheet PDF文件第6页浏览型号SN54HC563WR的Datasheet PDF文件第7页 
SN54HC563, SN74HC563  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS145B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC563 . . . J OR W PACKAGE  
SN74HC563 . . . DW OR N PACKAGE  
(TOP VIEW)  
High-Current 3-State Outputs Drive Bus  
Lines Directly or up to 15 LSTTL Loads  
Bus-Structured Pinout  
Package Options Include Plastic  
Small-Outline (DW) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
description  
13 7Q  
12 8Q  
These 8-bit transparent D-type latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
11  
GND  
LE  
SN54HC563 . . . FK PACKAGE  
(TOP VIEW)  
While the latch-enable (LE) input is high, the  
Q outputs follow the complements of the data (D)  
inputs. When LE is taken low, the outputs are  
latched at the inverses of the levels set up at the  
D inputs.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased high logic  
level provide the capability to drive bus lines  
without interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54HC563 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC563 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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