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SN54HC161J PDF预览

SN54HC161J

更新时间： 2024-09-30 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
14页 203K
描述
4-BIT SYNCHRONOUS BINARY COUNTERS

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SN54HC161J 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：16 weeks
风险等级：0.98Is Samacsys：N
其他特性：RCO OUTPUT计数方向：UP
系列：HC/UHJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：21000000 Hz最大I（ol）：0.0052 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：46 ns
传播延迟（tpd）：310 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.92 mm
最小 fmax：25 MHzBase Number Matches：1

SN54HC161J 数据手册

 浏览型号SN54HC161J的Datasheet PDF文件第2页浏览型号SN54HC161J的Datasheet PDF文件第3页浏览型号SN54HC161J的Datasheet PDF文件第4页浏览型号SN54HC161J的Datasheet PDF文件第5页浏览型号SN54HC161J的Datasheet PDF文件第6页浏览型号SN54HC161J的Datasheet PDF文件第7页 
SN54HC161, SN74HC161  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCLS297A – JANUARY 1996 – REVISED MAY 1997  
SN54HC161 . . . J OR W PACKAGE  
SN74HC161 . . . D OR N PACKAGE  
(TOP VIEW)  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT  
ENP  
GND  
LOAD  
description  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. The ’HC161 are  
4-bit binary counters. Synchronous operation is  
provided by having all flip-flops clocked  
simultaneously so that the outputs change  
coincident with each other when so instructed by  
the count-enable (ENP, ENT) inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes that are normally  
associated with synchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock waveform.  
SN54HC161 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
Q
C
D
D
9 10 11 12 13  
These counters are fully programmable; that is,  
they can be preset to any number between 0 and  
9 or 15. As presetting is synchronous, setting up  
a low level at the load input disables the counter  
and causes the outputs to agree with the setup  
data after the next clock pulse, regardless of the  
levels of the enable inputs.  
NC – No internal connection  
The clear function for the ’HC161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop  
outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The SN54HC161 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC161 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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SN54HC161J 替代型号

型号 品牌 替代类型 描述 数据表
8407501EA TI

完全替代

 4-BIT SYNCHRONOUS BINARY COUNTERS
CD74HC161M TI

完全替代

 High Speed CMOS Logic Presettable Counters
CD74HC161E TI

完全替代

 High Speed CMOS Logic Presettable Counters

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SN54HC161J-00 TI

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
SN54HC161-SP TI

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 		同步 4 位二进制计数器
SN54HC161W TI

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 		4-BIT SYNCHRONOUS BINARY COUNTERS
SN54HC161WR TI

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 		暂无描述
SN54HC162 TI

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 		SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SN54HC162FH TI

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 		IC,COUNTER,UP,DECADE,HC-CMOS,LLCC,20PIN,CERAMIC
SN54HC162FK TI

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CQCC20, CERAMIC, LCC-20
SN54HC162FK-00 TI

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CQCC20
SN54HC162J ROCHESTER

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 		Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, C
SN54HC162J TI

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, 0.300 INCH, CER

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