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SN54F51J PDF预览

SN54F51J

更新时间: 2024-11-24 20:40:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 输入元件逻辑集成电路
页数 文件大小 规格书
5页 79K
描述
AND-OR-Invert Gate, F/FAST Series, 2-Func, 6-Input, TTL, CDIP14, 0.300 INCH, CERAMIC, DIP-14

SN54F51J 技术参数

生命周期:Contact Manufacturer包装说明:0.300 INCH, CERAMIC, DIP-14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.76其他特性:ASYMMETRICAL INPUTS
系列:F/FASTJESD-30 代码:R-GDIP-T14
长度:19.56 mm逻辑集成电路类型:AND-OR-INVERT GATE
功能数量:2输入次数:6
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):5 ns
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54F51J 数据手册

 浏览型号SN54F51J的Datasheet PDF文件第2页浏览型号SN54F51J的Datasheet PDF文件第3页浏览型号SN54F51J的Datasheet PDF文件第4页浏览型号SN54F51J的Datasheet PDF文件第5页 
ꢀꢁꢂ ꢃ ꢄ ꢂ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢄꢂ ꢅ  
ꢉꢊ ꢋꢌꢇ ꢍ ꢎꢏ ꢐ ꢉꢑꢇ ꢍ ꢎꢐꢁꢒ ꢊꢓꢆꢇ ꢍ ꢎꢏ ꢐꢉꢑ ꢇꢔ ꢎꢐ ꢁꢒꢊꢓ ꢇꢋꢁꢉ ꢎꢕꢖ ꢎꢐꢁꢗ ꢑꢖꢓꢇ ꢘ ꢋꢓꢑ ꢀ  
SDFS092 − JANUARY 1989 − REVISED OCTOBER 1993  
SN54F51 . . . J PACKAGE  
SN74F51 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1A  
2A  
2B  
2C  
2D  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1B  
1F  
1E  
1D  
1Y  
description  
These devices contain 2-wide 2-input and 2-wide  
3-input AND-OR-INVERT gates. They perform  
the following Boolean functions:  
2Y  
GND  
8
1Y = (1A 1B 1C) + (1D 1E 1F)  
2Y = (2A 2B) + (2C 2D)  
SN54F51 . . . FK PACKAGE  
(TOP VIEW)  
The SN54F51 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F51 is characterized for  
operation from 0°C to 70°C.  
3
2
1
20 19  
18  
2B  
NC  
2C  
NC  
2D  
1B  
NC  
1F  
4
5
6
7
8
FUNCTION TABLES  
GATE 1  
17  
16  
15 NC  
14  
INPUTS  
OUTPUT  
1Y  
1E  
1A  
H
1B  
H
1C  
1D  
X
1E  
X
1F  
X
9 10 11 12 13  
H
X
L
L
X
X
H
H
H
All other combinations  
H
NC − No internal connection  
GATE 2  
INPUTS  
OUTPUT  
2Y  
2A  
H
2B  
H
2C  
X
2D  
X
L
L
X
X
H
H
All other combinations  
H
ꢓꢦ  
Copyright 1993, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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