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SN54F520J PDF预览

SN54F520J

更新时间: 2024-11-23 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 运算电路逻辑集成电路输入元件
页数 文件大小 规格书
5页 77K
描述
8-BIT IDENTITY COMPARATORS

SN54F520J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, CERAMIC, DIP-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:N其他特性:WITH PULL-UP RESISTORS ON B INPUTS; CASCADABLE
系列:F/FASTJESD-30 代码:R-GDIP-T20
长度:24.195 mm负载电容(CL):50 pF
逻辑集成电路类型:IDENTITY COMPARATOR位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):32 mA传播延迟(tpd):11.3 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN54F520J 数据手册

 浏览型号SN54F520J的Datasheet PDF文件第2页浏览型号SN54F520J的Datasheet PDF文件第3页浏览型号SN54F520J的Datasheet PDF文件第4页浏览型号SN54F520J的Datasheet PDF文件第5页 
SN54F520, SN74F520  
8-BIT IDENTITY COMPARATORS  
SDFS081A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F520 . . . J PACKAGE  
SN74F520 . . . DW OR N PACKAGE  
(TOP VIEW)  
Compares Two 8-Bit Words  
20-kPullup Resistors on Q Inputs  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
OE  
P0  
Q0  
P1  
Q1  
P2  
Q2  
P3  
Q3  
V
CC  
P = Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Q7  
P7  
Q6  
P6  
description  
These identity comparators perform comparisons  
on two 8-bit binary or BCD words. They provide  
P = Q outputs. The F520 features 20-kpullup  
termination resistors on the Q inputs for analog or  
switch data.  
Q5  
13 P5  
12 Q4  
11  
GND  
P4  
The SN54F520 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F520 is characterized for  
operation from 0°C to 70°C.  
SN54F520 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
3
2
1
20 19  
18  
INPUTS  
OUTPUT  
P = Q  
Q7  
P7  
Q6  
P6  
Q5  
P1  
Q1  
P2  
Q2  
P3  
4
5
6
7
8
P, Q  
OE  
L
17  
16  
15  
14  
P = Q  
P Q  
X
L
H
H
X
H
9 10 11 12 13  
logic symbol  
COMP  
1
OE  
2
P0  
0
4
P1  
6
P2  
8
P3  
11  
P
P4  
13  
P5  
15  
P6  
17  
P7  
3
7
0
19  
P = Q  
1P = Q  
Q0  
5
Q1  
7
Q2  
9
Q3  
12  
Q4  
14  
Q5  
16  
Q6  
18  
Q7  
Q
7
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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