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SN54CDC586

更新时间： 2024-11-15 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 驱动器时钟
页数 文件大小 规格书
11页 152K
描述
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUPUTS

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SN54CDC586 数据手册

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SN54CDC586  
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER  
WITH 3-STATE OUPUTS  
SGBS311 – FEBRUARY 1997  
WD PACKAGE  
(TOP VIEW)  
Low Output Skew for Clock-Distribution  
and Clock-Generation Applications  
Operates at 3.3-V V  
CC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
Distributes One Clock Input to Twelve  
Outputs  
2
AV  
CLKIN  
NC  
CC  
3
AGND  
Two Select Inputs Configure Up to Nine  
Outputs to Operate at One-Half or Double  
the Input Frequency  
4
FBIN  
AGND  
SEL0  
SEL1  
GND  
GND  
1Y1  
AV  
CC  
5
OE  
6
TEST  
CLR  
No External RC Network Required  
7
External Feedback Pin (FBIN) Is Used to  
Synchronize the Outputs to the Clock Input  
8
V
CC  
9
4Y3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
Application for Synchronous DRAM,  
High-Speed Microprocessor  
V
V
CC  
CC  
GND  
1Y2  
4Y2  
TTL-Compatible Inputs and Outputs  
GND  
Outputs Drive Parallel 50-Ω Terminated  
Transmission Lines  
V
V
CC  
CC  
GND  
1Y3  
4Y1  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
GND  
GND  
V
CC  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
GND  
GND  
2Y1  
V
CC  
3Y3  
Packaged in 56-Pin Ceramic Flat Package  
GND  
V
V
CC  
CC  
description  
GND  
2Y2  
3Y2  
GND  
The SN54CDC586 is  
a high-performance,  
V
V
CC  
CC  
low-skew, low-jitter clock driver. It uses a  
phase-lock loop (PLL) to precisely align, in both  
frequency and phase, the clock output signals to  
the clock input (CLKIN) signal. It is specifically  
designed for use with popular microprocessors  
operating at speeds from 50 MHz to 100 MHz, or  
down to 25 MHz on outputs configured as  
half-frequency outputs. The SN54CDC586  
GND  
2Y3  
3Y1  
GND  
GND  
NC  
V
CC  
NC  
NC – No internal connection  
operates at 3.3-V V  
properly terminated 50- transmission line.  
and is designed to drive a  
CC  
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of  
the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input  
andtheoutputs. TheoutputusedasthefeedbackpinissynchronizedtothesamefrequencyastheCLKINinput.  
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs  
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN  
frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are  
adjusted to 50%, independent of the duty cycle at CLKIN.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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