SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
SN54F00 . . . J PACKAGE
SN74F00 . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = A • B or Y = A + B in positive logic.
2Y
GND
8
The SN54F00 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F00 is characterized for
operation from 0°C to 70°C.
SN54F00 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each gate)
3
2
1
20 19
18
INPUTS
OUTPUT
Y
1Y
NC
2A
4
5
6
7
8
4A
NC
4Y
NC
3B
A
B
H
X
L
17
16
15
14
H
L
L
H
H
NC
2B
X
9 10 11 12 13
†
logic symbol
1
1A
2
&
3
6
NC – No internal connection
1Y
2Y
3Y
4Y
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
8
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
1
2
1A
1B
3
1Y
2Y
3Y
4Y
4
5
2A
2B
6
8
9
3A
3B
10
12
13
4A
4B
11
Pin numbers shown are for the D, J, and N packages.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–3
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