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SN54BCT373_08 PDF预览

SN54BCT373_08

更新时间: 2024-11-24 04:31:23
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德州仪器 - TI 锁存器输出元件
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18页 698K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54BCT373_08 数据手册

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SN54BCT373, SN74BCT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
State-of-the-Art BiCMOS Design  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
Significantly Reduces I  
ESD Protection Exceeds JESD 22  
CCZ  
– 2000-V Human-Body Model (A114-A)  
Full Parallel Access for Loading  
SN54BCT373 . . . J OR W PACKAGE  
SN74BCT373 . . . DB, DW, N, OR NS PACKAGE  
(TOP VIEW)  
SN54BCT373 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
GND  
description/ordering information  
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is  
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched  
at the logic levels that were set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74BCT373N  
SN74BCT373N  
Tube  
SN74BCT373DW  
SN74BCT373DWR  
SN74BCT373NSR  
SN74BCT373DBR  
SNJ54BCT373J  
SNJ54BCT373W  
SNJ54BCT373FK  
SOIC – DW  
BCT373  
0°C to 70°C  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
SSOP – DB  
CDIP – J  
BCT373  
BT373  
SNJ54BCT373J  
SNJ54BCT373W  
SNJ54BCT373FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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