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SN54AHC16374_08

更新时间： 2024-11-16 05:18:23
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德州仪器 - TI 触发器输出元件
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14页 400K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54AHC16374_08 数据手册

 浏览型号SN54AHC16374_08的Datasheet PDF文件第2页浏览型号SN54AHC16374_08的Datasheet PDF文件第3页浏览型号SN54AHC16374_08的Datasheet PDF文件第4页浏览型号SN54AHC16374_08的Datasheet PDF文件第5页浏览型号SN54AHC16374_08的Datasheet PDF文件第6页浏览型号SN54AHC16374_08的Datasheet PDF文件第7页 
SN54AHC16374, SN74AHC16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCLS330G – MARCH 1996 – REVISED JANUARY 2000  
SN54AHC16374 . . . WD PACKAGE  
SN74AHC16374 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1
2
3
4
5
6
7
8
9
48  
Operating Range 2-V to 5.5-V V  
CC  
47 1D1  
46 1D2  
45 GND  
44 1D3  
43 1D4  
3-State Outputs Drive Bus Lines Directly  
Distributed V and GND Pins Minimize  
CC  
High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
V
42  
V
CC  
CC  
1Q5  
1Q6  
41 1D5  
40 1D6  
39 GND  
38 1D7  
37 1D8  
36 2D1  
35 2D2  
34 GND  
33 2D3  
32 2D4  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND 10  
1Q7 11  
1Q8 12  
2Q1 13  
2Q2 14  
GND 15  
2Q3 16  
2Q4 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
18  
31  
V
CC  
CC  
2Q5 19  
2Q6 20  
GND 21  
2Q7 22  
2Q8 23  
2OE 24  
30 2D5  
29 2D6  
28 GND  
27 2D7  
26 2D8  
25 2CLK  
description  
The  
’AHC16374  
devices  
are  
16-bit  
edge-triggered D-type flip-flops with 3-state  
outputs designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock  
(CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54AHC16374 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC16374 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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