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SN10KHT5574NTE4 PDF预览

SN10KHT5574NTE4

更新时间: 2024-11-29 21:15:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件接口集成电路锁存器
页数 文件大小 规格书
9页 159K
描述
IC OCTAL ECL TO TTL TRANSLATOR, TRUE OUTPUT, PDIP24, ROHS COMPLIANT, PLASTIC, DIP-24, Level Translator

SN10KHT5574NTE4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP24,.3
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.79最大延迟:7.4 ns
接口集成电路类型:ECL TO TTL TRANSLATORJESD-30 代码:R-PDIP-T24
长度:31.64 mm标称负供电电压:-5.2 V
位数:1功能数量:8
端子数量:24最高工作温度:75 °C
最低工作温度:输出特性:3-STATE
输出锁存器或寄存器:REGISTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5,-5.2 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Level Translators
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:BIPOLAR温度等级:COMMERCIAL EXTENDED
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN10KHT5574NTE4 数据手册

 浏览型号SN10KHT5574NTE4的Datasheet PDF文件第2页浏览型号SN10KHT5574NTE4的Datasheet PDF文件第3页浏览型号SN10KHT5574NTE4的Datasheet PDF文件第4页浏览型号SN10KHT5574NTE4的Datasheet PDF文件第5页浏览型号SN10KHT5574NTE4的Datasheet PDF文件第6页浏览型号SN10KHT5574NTE4的Datasheet PDF文件第7页 
ꢊ ꢋꢆꢌꢍꢎꢏ ꢋꢍ ꢐꢆꢊ ꢐꢆ ꢆꢍꢎꢆ ꢑꢌ ꢁꢀꢍ ꢌꢆꢊ ꢑꢎꢒ ꢓ ꢆ ꢅꢎ ꢔ ꢐꢆꢕ ꢖ  
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990  
DW OR NT PACKAGE  
(TOP VIEW)  
10KH Compatible  
ECL Clock and TTL Control Inputs  
1Q  
2Q  
3Q  
4Q  
1D  
2D  
3D  
4D  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Flow-Through Architecture Optimizes PCB  
2
Layout  
3
Center Pin V , V , and GND  
4
CC EE  
V
OE(TTL)  
5
Configurations Minimize High-Speed  
CC  
GND  
V
6
Switching Noise  
EE  
GND  
GND  
5Q  
GND  
CLK(ECL)  
5D  
7
Package Options Include “Small Outline”  
8
Packages and Standard Plastic DIPs  
9
6Q  
7Q  
8Q  
6D  
7D  
8D  
10  
11  
12  
description  
This octal ECL-to-TTL translator is designed to  
provide efficient translation between a 10KH ECL  
signal environment and a TTL signal environment.  
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented  
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the  
clock, the Q outputs are set to the logic levels that were set up at the D inputs.  
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive  
bus lines without need for interface or pullup components.  
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained  
or new data can be entered while the outputs are off.  
The SN10KHT5574 is characterized for operation from 0°C to 75°C.  
FUNCTION TABLE  
OUTPUT  
INPUTS  
(TTL)  
OE  
L
CLK  
D
L
Q
L
L
H
X
X
H
Q
L
L
o
H
X
Z
ꢆꢦ  
Copyright 1990, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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