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SN0305042RTHT PDF预览

SN0305042RTHT

更新时间： 2024-11-16 11:07:55
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动输出元件逻辑集成电路时钟驱动器
页数 文件大小 规格书
24页 580K
描述
1:3 LVPECL 时钟缓冲器 + LVCMOS 输出 + 可编程分频器 | RGE | 24 | -40 to 85

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SN0305042RTHT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.38其他特性：3 LVPECL DIFFERENTIAL CLOCK OUTPUTS AND SINGLE ENDED LVCMOS OUTPUT
系列：1803输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-N24JESD-609代码：e4
长度：4 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：2
功能数量：1反相输出次数：
端子数量：24实输出次数：4
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260传播延迟（tpd）：2.6 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.03 ns
座面最大高度：1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
最小 fmax：800 MHzBase Number Matches：1

SN0305042RTHT 数据手册

 浏览型号SN0305042RTHT的Datasheet PDF文件第2页浏览型号SN0305042RTHT的Datasheet PDF文件第3页浏览型号SN0305042RTHT的Datasheet PDF文件第4页浏览型号SN0305042RTHT的Datasheet PDF文件第5页浏览型号SN0305042RTHT的Datasheet PDF文件第6页浏览型号SN0305042RTHT的Datasheet PDF文件第7页 
CDCM1804  
www.ti.com  
SCAS697E–JULY 2003–REVISED MAY 2005  
1:3 LVPECL CLOCK BUFFER + ADDITIONAL  
LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER  
The CDCM1804 is characterized for operation from  
–40°C to 85°C.  
FEATURES  
•
Distributes One Differential Clock Input to  
Three LVPECL Differential Clock Outputs and  
One LVCMOS Single-Ended Output  
For use in single-ended driver applications, the  
CDCM1804 also provides a VBB output terminal that  
can be directly connected to the unused input as a  
common-mode voltage reference.  
•
•
Programmable Output Divider for Two  
LVPECL Outputs and LVCMOS Output  
Low-Output Skew 15 ps (Typical) for  
Clock-Distribution Applications for LVPECL  
Outputs; 1.6-ns Output Skew Between  
LVCMOS and LVPECL Transitions Minimizing  
Noise  
RGE PACKAGE  
(TOP VIEW)  
•
•
VCC Range 3 V–3.6 V  
24 23 22 21 20 19  
EN  
PECL  
IN  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
S0  
Signaling Rate Up to 800-MHz LVPECL and  
200-MHz LVCMOS  
V
V
V
DD  
1
DD  
•
•
Differential Input Stage for Wide  
Common-Mode Range  
Y1  
Y1  
(1)  
SS  
V
IN  
Provides VBB Bias Voltage Output for  
Single-Ended Input Signals  
PECL  
VBB  
V
DD  
V
DD  
1
3
DD  
•
•
•
Receiver Input Threshold ±75 mV  
7
8
9
10 11 12  
24-Terminal QFN Package (4 mm × 4 mm)  
Accepts Any Differential Signaling:  
LVDS, HSTL, CML, VML, SSTL-2, and  
Single-Ended: LVTTL/LVCMOS  
(1)  
Thermal pad must be connected to V  
.
SS  
P0024-01  
DESCRIPTION  
RTH PACKAGE  
(TOP VIEW)  
The CDCM1804 clock driver distributes one pair of  
differential clock inputs to three pairs of LVPECL  
differential clock outputs Y[2:0] and Y[2:0], with mini-  
mum skew for clock distribution. The CDCM1804 is  
specifically designed for driving 50-Ω transmission  
lines. Additionally, the CDCM1804 offers  
a
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
EN  
PECL  
IN  
S0  
V
single-ended LVCMOS output Y3. This output is  
delayed by 1.6 ns over the three LVPECL output  
stages to minimize noise impact during signal tran-  
sitions.  
V
1
DD  
DD  
Y1  
Y1  
(1)  
SS  
V
IN  
The CDCM1804 has three control terminals, S0, S1,  
and S2, to select different output mode settings. The  
S[2:0] terminals are 3-level inputs and therefore allow  
up to 33 = 27 combinations. Additionally, an enable  
terminal (EN) is provided to disable or enable all  
outputs simultaneously. The EN terminal is a 3-level  
input as well and extends the number of settings to  
2 × 27 = 54. See Table 1 for details.  
V
DD  
PECL  
VBB  
V
DD  
V
DD  
1
3
(1)  
Thermal pad must be connected to V  
.
SS  
P0025-01  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...24

中文翻译

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SN0305042RTHT 替代型号

型号 品牌 替代类型 描述 数据表
SN0305042RTHR TI

完全替代

 1:3 LVPECL 时钟缓冲器 + LVCMOS 输出 + 可编程分频器 | RGE |

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